18096906. BLOCK LEVEL DESIGN METHOD FOR HETEROGENEOUS PG-STRUCTURE CELLS simplified abstract (Taiwan Semiconductor Manufacturing Co., Ltd.)
BLOCK LEVEL DESIGN METHOD FOR HETEROGENEOUS PG-STRUCTURE CELLS
Organization Name
Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor(s)
Yen-Hung Lin of Hsinchu City (TW)
Yuan-Te Hou of Hsinchu City (TW)
Chung-Hsing Wang of Hsinchu County (TW)
BLOCK LEVEL DESIGN METHOD FOR HETEROGENEOUS PG-STRUCTURE CELLS - A simplified explanation of the abstract
This abstract first appeared for US patent application 18096906 titled 'BLOCK LEVEL DESIGN METHOD FOR HETEROGENEOUS PG-STRUCTURE CELLS
Simplified Explanation
The abstract describes a method for partitioning a group of power-ground (PG) cells in a circuit design. The method involves placing out-boundary PG cells on a substrate, aligning their power strips with corresponding power rails on the substrate. Similarly, in-boundary PG cells are also placed on the substrate, aligning their power strips with the power rails.
- The method involves partitioning power-ground (PG) cells in a circuit design.
- Out-boundary PG cells are placed on a substrate, aligning their power strips with corresponding power rails on the substrate.
- In-boundary PG cells are also placed on the substrate, aligning their power strips with the power rails.
Potential Applications
This technology can be applied in various fields where circuit design and partitioning of power-ground cells are required. Some potential applications include:
- Integrated circuit design
- Electronics manufacturing
- Semiconductor industry
Problems Solved
The method addresses the following problems in circuit design:
- Efficient partitioning of power-ground cells
- Alignment of power strips with power rails
- Ensuring proper functioning and connectivity of power-ground cells
Benefits
The method offers several benefits in circuit design and power-ground cell partitioning:
- Improved efficiency in partitioning power-ground cells
- Enhanced connectivity and alignment of power strips with power rails
- Simplified circuit design process
- Increased reliability and functionality of the circuit design
Original Abstract Submitted
A partitioning method for partitioning a group of power-ground (PG) cells is disclosed. The method includes: placing at least one out-boundary PG cell on a substrate, wherein power strips of the at least one out-boundary PG cell are aligned with corresponding power rails on the substrate; and placing at least one in-boundary PG cell on the substrate, wherein power strips of the at least one in-boundary PG cell are aligned with corresponding power rails on the substrate.
