17655321. Integration of Multiple Transistors Having Fin and Mesa Structures simplified abstract (Taiwan Semiconductor Manufacturing Co., Ltd.)
Integration of Multiple Transistors Having Fin and Mesa Structures
Organization Name
Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor(s)
Ru-Shang Hsiao of Jhubei City (TW)
Ching-Hwanq Su of Tainan City (TW)
Chen-Bin Lin of Tainan City (TW)
Wen-Hsin Chan of Zhubei City (TW)
Integration of Multiple Transistors Having Fin and Mesa Structures - A simplified explanation of the abstract
This abstract first appeared for US patent application 17655321 titled 'Integration of Multiple Transistors Having Fin and Mesa Structures
Simplified Explanation
The patent application describes a structure that includes a bulk semiconductor substrate, dielectric isolation regions, semiconductor fins, and gate stacks. The gate stacks are arranged in a way that their top surfaces are coplanar with each other.
- The structure includes a bulk semiconductor substrate.
- A first plurality of dielectric isolation regions is present over the bulk semiconductor substrate.
- A plurality of semiconductor fins protrude higher than the first plurality of dielectric isolation regions.
- A first gate stack is located on top surfaces and sidewalls of the semiconductor fins.
- A second plurality of dielectric isolation regions is present over the bulk semiconductor substrate.
- A mesa structure is formed in the second plurality of dielectric isolation regions.
- A second gate stack is positioned over the mesa structure.
- The top surfaces of the first gate stack and the second gate stack are coplanar with each other.
Potential Applications
This technology has potential applications in the field of semiconductor manufacturing and integrated circuit design.
Problems Solved
The structure described in the patent application solves the problem of achieving coplanarity between different gate stacks in a semiconductor device.
Benefits
The coplanarity of the gate stacks allows for improved performance and reliability of the semiconductor device. It also simplifies the manufacturing process and reduces the complexity of the device design.
Original Abstract Submitted
A structure includes a bulk semiconductor substrate, a first plurality of dielectric isolation regions over the bulk semiconductor substrate, a plurality of semiconductor fins protruding higher than the first plurality of dielectric isolation regions, a first gate stack on top surfaces and sidewalls of the plurality of semiconductor fins, a second plurality of dielectric isolation regions over the bulk semiconductor substrate, a mesa structure in the second plurality of dielectric isolation regions, and a second gate stack over the mesa structure. Top surfaces of the first gate stack and the second gate stack are coplanar with each other.
