17690728. BIT-LINE RESISTANCE REDUCTION simplified abstract (Taiwan Semiconductor Manufacturing Co., Ltd.)

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BIT-LINE RESISTANCE REDUCTION

Organization Name

Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor(s)

Yu-Feng Yin of Hsinchu County (TW)

Min-Kun Dai of Hsinchu City (TW)

Chien-Hua Huang of Toufen Township (TW)

Chung-Te Lin of Tainan City (TW)

BIT-LINE RESISTANCE REDUCTION - A simplified explanation of the abstract

This abstract first appeared for US patent application 17690728 titled 'BIT-LINE RESISTANCE REDUCTION

Simplified Explanation

The present disclosure is about an integrated chip structure that includes a memory array with multiple memory devices arranged in rows and columns.

  • The integrated chip structure has a word-line connected to a set of memory devices in a row and a bit-line connected to a set of memory devices in a column.
  • A local interconnect runs parallel to the bit-line and is connected to the bit-line and two or more memory devices in the column.
  • The local interconnect is connected to the bit-line through multiple interconnect vias.

Potential applications of this technology:

  • Integrated chip structures can be used in various electronic devices such as smartphones, computers, and IoT devices.
  • The memory array can store and retrieve data, making it suitable for applications that require data storage and processing.

Problems solved by this technology:

  • The integrated chip structure allows for efficient connectivity between the memory devices and the bit-line through the local interconnect and interconnect vias.
  • It provides a compact and organized layout for the memory array, improving the overall performance and functionality of the integrated chip.

Benefits of this technology:

  • The integrated chip structure offers improved data transfer and access speeds due to the efficient connectivity between the memory devices and the bit-line.
  • The compact layout of the memory array allows for higher memory density, enabling more data to be stored in a smaller space.
  • The organized structure of the integrated chip enhances the overall reliability and functionality of the chip.


Original Abstract Submitted

The present disclosure relates integrated chip structure. The integrated chip structure includes a memory array having a plurality of memory devices arranged in a plurality of rows and a plurality of columns. A word-line is coupled to a first set of the plurality of memory devices disposed within a first row of the plurality of rows. A bit-line is coupled to a second set of the plurality of memory devices disposed within a first column of the plurality of columns. A local interconnect extends in parallel to the bit-line and is coupled to the bit-line and two or more of the second set of the plurality of memory devices. The local interconnect is coupled to the bit-line by a plurality of interconnect vias that are between the local interconnect and the bit-line.

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