18151014. Redistribution Lines Having Nano Columns and Method Forming Same simplified abstract (Taiwan Semiconductor Manufacturing Co., Ltd.)

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Redistribution Lines Having Nano Columns and Method Forming Same

Organization Name

Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor(s)

Po-Hao Tsai of Taoyuan City (TW)

Ming-Da Cheng of Taoyuan City (TW)

Wen-Hsiung Lu of Tainan City (TW)

Hsu-Lun Liu of Tainan City (TW)

Kai-Di Wu of Tainan City (TW)

Su-Fei Lin of Tainan City (TW)

Redistribution Lines Having Nano Columns and Method Forming Same - A simplified explanation of the abstract

This abstract first appeared for US patent application 18151014 titled 'Redistribution Lines Having Nano Columns and Method Forming Same

Simplified Explanation

The patent application describes a method for forming conductive features on a wafer using a plating process. The method involves the following steps:

1. A seed layer is formed over a first conductive feature on the wafer. 2. A patterned plating mask is created on the seed layer. 3. A second conductive feature is plated in an opening of the patterned plating mask. 4. The plating process consists of multiple plating cycles. 5. Each plating cycle includes a first plating process performed at a high current density. 6. Each plating cycle also includes a second plating process performed at a lower current density. 7. The patterned plating mask is then removed. 8. The seed layer is etched.

  • The method involves plating conductive features on a wafer using a seed layer and a patterned plating mask.
  • The plating process consists of multiple cycles, each with a high current density and a low current density.
  • The patterned plating mask is removed after the plating process.
  • The seed layer is etched to complete the process.

Potential Applications

  • This method can be used in the semiconductor industry for fabricating integrated circuits.
  • It can be applied in the production of microchips and other electronic devices.

Problems Solved

  • The method provides a more controlled and efficient plating process for forming conductive features on a wafer.
  • It helps in achieving precise and uniform plating of the second conductive feature.
  • The use of multiple plating cycles with different current densities improves the quality and reliability of the conductive features.

Benefits

  • The method allows for the formation of high-quality conductive features on a wafer.
  • It reduces the risk of defects and inconsistencies in the plating process.
  • The use of different current densities in the plating cycles improves the overall efficiency and accuracy of the process.


Original Abstract Submitted

A method includes forming a seed layer over a first conductive feature of a wafer, forming a patterned plating mask on the seed layer, and plating a second conductive feature in an opening in the patterned plating mask. The plating includes performing a plurality of plating cycles, with each of the plurality of plating cycles including a first plating process performed using a first plating current density, and a second plating process performed using a second plating current density lower than the first plating current density. The patterned plating mask is then removed, and the seed layer is etched.

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