18155932. FOUR CPP WIDE MEMORY CELL WITH BURIED POWER GRID, AND METHOD OF FABRICATING SAME simplified abstract (Taiwan Semiconductor Manufacturing Co., Ltd.)
FOUR CPP WIDE MEMORY CELL WITH BURIED POWER GRID, AND METHOD OF FABRICATING SAME
Organization Name
Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor(s)
Hidehiro Fujiwara of Hsinchu (TW)
Wei-Chang Zhao of Hsinchu (TW)
FOUR CPP WIDE MEMORY CELL WITH BURIED POWER GRID, AND METHOD OF FABRICATING SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18155932 titled 'FOUR CPP WIDE MEMORY CELL WITH BURIED POWER GRID, AND METHOD OF FABRICATING SAME
Simplified Explanation
The abstract describes a memory device that includes various structures and components for efficient data storage and retrieval. Here is a simplified explanation of the abstract:
- The memory device consists of active regions and gate structures, where each gate structure is connected to a specific portion of an active region.
- Contact-to-transistor-component structures (MD structures) are positioned over another portion of the active regions, with one MD structure placed between adjacent gate structures.
- Via-to-gate/MD (VGD) structures are located over the corresponding gate electrode and MD structure, providing a connection between them.
- Conductive segments are present over and electrically connected to each VGD structure, facilitating the flow of electrical signals.
- Buried contact-to-transistor-component structures (BVD) structures are positioned beneath a third portion of the active regions.
- Buried conductive segments are located under each BVD structure, serving as additional electrical connections.
Potential applications of this technology:
- Memory devices in electronic devices such as smartphones, tablets, and computers.
- Storage systems in data centers and servers.
- Embedded memory in various electronic components.
Problems solved by this technology:
- Efficient data storage and retrieval in memory devices.
- Enhanced connectivity between different components of the memory device.
- Optimization of space utilization within the memory device.
Benefits of this technology:
- Improved performance and speed of memory devices.
- Higher storage capacity in a compact form factor.
- Enhanced reliability and durability of the memory device.
Original Abstract Submitted
A memory device includes active regions and gate structures, each of the gate structures is electrically coupled to a first portion of a corresponding active region of the active regions. The memory device includes contact-to-transistor-component structures (MD structures), each of the MD structures is over a second portion of a corresponding active region, and a first MD structure is between adjacent gate structures. The memory device includes via-to-gate/MD (VGD) structures, each of the VGD structures is over to a corresponding gate electrode and MD structure. The memory device includes conductive segments, each of the conductive segments is over and electrically coupled to a corresponding VGD structure. The memory device includes buried contact-to-transistor-component structures (BVD) structures, each of the BVD structures is under a third portion of a corresponding active region. The memory device includes buried conductive segments, each of the buried conductive segments is under a corresponding BVD structure.
