17526774. SYSTEMS AND METHODS OF TESTING MEMORY DEVICES simplified abstract (Taiwan Semiconductor Manufacturing Co., Ltd.)

SYSTEMS AND METHODS OF TESTING MEMORY DEVICES

Organization Name

Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor(s)

Meng-Han Lin of Hsinchu City (TW)

Chia-En Huang of Xinfeng Township (TW)

SYSTEMS AND METHODS OF TESTING MEMORY DEVICES - A simplified explanation of the abstract

This abstract first appeared for US patent application 17526774 titled 'SYSTEMS AND METHODS OF TESTING MEMORY DEVICES

Simplified Explanation

The patent application describes a memory device that includes a first memory block with a memory sub-array and an interface portion. It also includes interconnect structures to connect the memory sub-array to transistors. Additionally, there are test structures next to the memory block to simulate electrical connections.

• The memory device includes a first memory block with a memory sub-array and an interface portion.
• It has interconnect structures to connect the memory sub-array to transistors.
• Test structures are included to simulate electrical connections of the interconnect structures.
• The test structures are electrically isolated from the memory block.

Potential Applications

• Memory devices for electronic devices such as computers, smartphones, and tablets.
• Data storage devices for servers and data centers.
• Embedded memory in various electronic systems.

Problems Solved

• Efficient testing of interconnect structures in memory devices.
• Simulating electrical connections without affecting the memory block.
• Ensuring proper functionality and reliability of memory devices.

Benefits

• Improved reliability and functionality of memory devices.
• Simplified testing process for interconnect structures.
• Enhanced performance and efficiency of memory devices.

Original Abstract Submitted

A memory device includes a first memory block. The first memory block includes a first memory sub-array and a first interface portion disposed next to the first memory sub-array. The first memory block further includes a plurality of first interconnect structures electrically coupled to the first memory sub-array through the first interface portion, and a second plurality of interconnect structures configured to electrically couple a corresponding one of the plurality of first interconnect structures to a transistor. The memory device further includes a first test structure and a second test structure disposed next to the first memory block, each configured to simulate electrical connections of the plurality of second interconnect structures. The first and second test structures are electrically coupled to each other and are each electrically isolated form the first memory block.