18151527. METHOD FOR LITHOGRAPHY IN SEMICONDUCTOR FABRICATION simplified abstract (Taiwan Semiconductor Manufacturing Co., Ltd.)

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METHOD FOR LITHOGRAPHY IN SEMICONDUCTOR FABRICATION

Organization Name

Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor(s)

Cheng-Kuan Wu of Hsinchu City (TW)

Po-Chung Cheng of Zhongpu Shiang (TW)

Li-Jui Chen of Hsinchu City (TW)

Chih-Tsung Shih of Hsinchu City (TW)

METHOD FOR LITHOGRAPHY IN SEMICONDUCTOR FABRICATION - A simplified explanation of the abstract

This abstract first appeared for US patent application 18151527 titled 'METHOD FOR LITHOGRAPHY IN SEMICONDUCTOR FABRICATION

Simplified Explanation

The abstract describes a method for lithography in semiconductor fabrication. Here are the key points:

  • The method involves placing a semiconductor wafer on a wafer stage.
  • An initial voltage is supplied to a set of electrodes on the wafer stage, which are electrically isolated from each other.
  • The topology of the semiconductor wafer is measured after the initial voltage is applied.
  • Based on the measured topology, different adjusted voltages are supplied to the electrodes of the wafer stage.

Potential applications of this technology:

  • Semiconductor fabrication: This method can be used in the manufacturing of semiconductors to improve the accuracy and precision of lithography processes.
  • Integrated circuit production: By optimizing the voltage distribution on the wafer stage, this method can help in producing high-quality integrated circuits with better performance.

Problems solved by this technology:

  • Topology variations: Semiconductor wafers can have variations in their topology, which can affect the accuracy of lithography processes. This method addresses this issue by adjusting the voltages on the wafer stage based on the measured topology.
  • Uniformity: By supplying different adjusted voltages to the electrodes, this method helps in achieving a more uniform distribution of voltage across the wafer, leading to improved lithography results.

Benefits of this technology:

  • Improved accuracy: By adjusting the voltages based on the measured topology, this method improves the accuracy of lithography processes, resulting in better quality semiconductor devices.
  • Enhanced performance: The optimized voltage distribution helps in producing integrated circuits with improved performance characteristics, such as faster processing speeds and lower power consumption.
  • Cost-effective: By addressing topology variations and improving uniformity, this method reduces the need for rework or scrap, leading to cost savings in semiconductor fabrication.


Original Abstract Submitted

A method for lithography in semiconductor fabrication is provided. The method includes placing a semiconductor wafer over a wafer stage. The method also includes supplying an initial voltage to a plurality of electrodes of the wafer stage based on a topology of the semiconductor wafer, wherein the electrodes of the wafer stage are electrically isolated from each other. The method further includes measuring an adjusted topology of the semiconductor wafer after the initial voltage is supplied. In addition, the method includes supplying different first adjusted voltages to the electrodes of the wafer stage according to the adjusted topology of the semiconductor wafer.

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