17650758. Heterogenous Integration Scheme for III-V/Si and Si CMOS Integrated Circuits simplified abstract (Taiwan Semiconductor Manufacturing Co., Ltd.)
Heterogenous Integration Scheme for III-V/Si and Si CMOS Integrated Circuits
Organization Name
Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor(s)
Chan-Hong Chern of Palo Alto CA (US)
Heterogenous Integration Scheme for III-V/Si and Si CMOS Integrated Circuits - A simplified explanation of the abstract
This abstract first appeared for US patent application 17650758 titled 'Heterogenous Integration Scheme for III-V/Si and Si CMOS Integrated Circuits
Simplified Explanation
The abstract describes a method for bonding a III-V die directly to a CMOS die to form a die stack. The III-V die includes a semiconductor substrate and a first circuit with a III-V based n-type transistor. The CMOS die includes a semiconductor substrate and a second circuit with an n-type transistor and a p-type transistor. The first circuit is electrically connected to the second circuit.
- III-V die is bonded directly to a CMOS die to form a die stack.
- III-V die includes a semiconductor substrate and a first circuit with a III-V based n-type transistor.
- CMOS die includes a semiconductor substrate and a second circuit with an n-type transistor and a p-type transistor.
- First circuit of the III-V die is electrically connected to the second circuit of the CMOS die.
Potential Applications
- Integrated circuits
- Semiconductor devices
- Electronics manufacturing
Problems Solved
- Integration of III-V and CMOS technologies
- Efficient electrical connections between different types of transistors
Benefits
- Improved performance and functionality of integrated circuits
- Enhanced efficiency and reliability of semiconductor devices
- Simplified manufacturing process for electronics
Original Abstract Submitted
A method includes bonding a III-V die directly to a Complementary Metal-Oxide-Semiconductor (CMOS) die to form a die stack. The III-V die includes a () semiconductor substrate, and a first circuit including a III-V based n-type transistor formed at a surface of the () semiconductor substrate. The CMOS die includes a () semiconductor substrate, and a second circuit including an n-type transistor and a p-type transistor on the () semiconductor substrate. The first circuit is electrically connected to the second circuit.
