18155392. Gate All Around Transistor Device and Fabrication Methods Thereof simplified abstract (Taiwan Semiconductor Manufacturing Co., Ltd.)

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Gate All Around Transistor Device and Fabrication Methods Thereof

Organization Name

Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor(s)

Chih-Ching Wang of Kinmen County (TW)

Chia-Ying Su of Hsinchu (TW)

Wen-Hsing Hsieh of Hsinchu City (TW)

Kuan-Lun Cheng of Hsin-Chu (TW)

Chung-Wei Wu of Hsin-Chu County (TW)

Zhiqiang Wu of Hsinchu County (TW)

Gate All Around Transistor Device and Fabrication Methods Thereof - A simplified explanation of the abstract

This abstract first appeared for US patent application 18155392 titled 'Gate All Around Transistor Device and Fabrication Methods Thereof

Simplified Explanation

The present disclosure describes a semiconductor device that includes vertically stacked suspended nanostructures on a substrate, with gate stacks and gate spacers engaging the nanostructures. The middle portion of the first suspended nanostructures has a larger thickness than the middle portion of the second suspended nanostructures.

  • The semiconductor device includes vertically stacked suspended nanostructures on a substrate.
  • The nanostructures are divided into two groups, with the first group having a larger thickness in the middle portion compared to the second group.
  • Each group of nanostructures is engaged by a gate stack and a gate spacer.
  • The device allows for precise control and manipulation of the nanostructures due to the difference in thickness between the two groups.

Potential Applications

  • This technology can be used in the development of advanced semiconductor devices.
  • It may find applications in the fields of electronics, telecommunications, and computing.

Problems Solved

  • The technology solves the problem of precise control and manipulation of suspended nanostructures in a semiconductor device.
  • It addresses the need for improved performance and functionality in semiconductor devices.

Benefits

  • The use of vertically stacked suspended nanostructures allows for increased device density and improved performance.
  • The difference in thickness between the two groups of nanostructures provides enhanced control and manipulation capabilities.
  • The technology enables the development of more advanced and efficient semiconductor devices.


Original Abstract Submitted

Embodiments of the present disclosure includes a semiconductor device. The semiconductor device includes first suspended nanostructures vertically stacked over one another and disposed on a substrate, a first gate stack engaging the first suspended nanostructures, a first gate spacer disposed on sidewalls of the first gate stack, second suspended nanostructures vertically stacked over one another and disposed on the substrate, a second gate stack engaging the second suspended nanostructures, and a second gate spacer disposed on sidewalls of the second gate stack. A middle portion of the first suspended nanostructures has a first thickness measured in a direction perpendicular to a top surface of the substrate. A middle portion of the second suspended nanostructures has a second thickness measured in the direction. The second thickness is smaller than the first thickness.