18156912. CELL LAYOUT OF SEMICONDUCTOR DEVICE simplified abstract (Taiwan Semiconductor Manufacturing Co., Ltd.)

CELL LAYOUT OF SEMICONDUCTOR DEVICE

Organization Name

Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor(s)

Yi-Lin Chuang of Taipei City (TW)

Huang-Yu Chen of Hsinchu County (TW)

Yun-Han Lee of Hsinchu County (TW)

CELL LAYOUT OF SEMICONDUCTOR DEVICE - A simplified explanation of the abstract

This abstract first appeared for US patent application 18156912 titled 'CELL LAYOUT OF SEMICONDUCTOR DEVICE

Simplified Explanation

The patent application describes a device that includes a pin and multiple metal interconnects stacked over the pin. The interconnects are electrically coupled to each other and form an equivalent tapping point of the pin. The device is fabricated after passing a simulation test.

• The device includes a pin and multiple metal interconnects.
• The metal interconnects are stacked over the pin and electrically coupled to each other.
• The interconnects form an equivalent tapping point of the pin.
• Fabrication of the device is initiated after passing a simulation test.
• The first metal interconnect has a different width than the second metal interconnects.

Potential applications of this technology:

• Integrated circuits and semiconductor devices
• Electronics manufacturing

Problems solved by this technology:

• Efficient and reliable electrical coupling of metal interconnects
• Accurate fabrication of the device after passing simulation tests

Benefits of this technology:

• Improved performance and functionality of integrated circuits
• Enhanced reliability and durability of semiconductor devices
• Streamlined manufacturing process for electronics

Original Abstract Submitted

A device is disclosed. The cell block includes a pin disposed at a Nth metal layer in a cell layout. The first metal interconnect is disposed at a (N+1)th metal layer above the Nth metal layer and stacked over the pin, and electrically coupled to the pin. The second interconnects are disposed at a (N+2)th metal layer and stacked over the first metal interconnect, and parallel to each other. The second metal interconnects are electrically coupled to the first metal interconnect, and forming an equivalent tapping point of the pin of the cell block. The equivalent tapping point and the pin are vertically overlapped with each other, and fabrication of the device is initiated after a DRC or a SEM simulation test is passed. A first width of at least one first metal interconnect is different from a second width of one of the plurality of second metal interconnects.