18149509. 3D Package Structure and Methods of Forming Same simplified abstract (Taiwan Semiconductor Manufacturing Co., Ltd.)

3D Package Structure and Methods of Forming Same

Organization Name

Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor(s)

Meng-Tse Chen of Changzhi Township (TW)

Chung-Shi Liu of Hsinchu (TW)

Chih-Wei Lin of Zhubei City (TW)

Hui-Min Huang of Taoyuan City (TW)

Hsuan-Ting Kuo of Taichung City (TW)

Ming-Da Cheng of Taoyuan City (TW)

3D Package Structure and Methods of Forming Same - A simplified explanation of the abstract

This abstract first appeared for US patent application 18149509 titled '3D Package Structure and Methods of Forming Same

Simplified Explanation

The abstract describes a method for forming a multi-layered package for electronic devices. Here are the key points:

• The method involves creating a first die package on a carrier substrate, which includes a first die.
• A redistribution layer is formed over the first die, consisting of metal layers embedded in dielectric layers.
• A second die is adhered to the redistribution layer.
• A first dielectric material is laminated over the second die and the first redistribution layer.
• First vias are formed through the first dielectric material to connect to the second die, and second vias are formed to connect to the first redistribution layer.
• Finally, a second redistribution layer is formed over the first dielectric material, connecting to the first and second vias.

Potential applications of this technology:

• This method can be used in the manufacturing of electronic devices, such as integrated circuits or microprocessors.
• It allows for the integration of multiple dies within a single package, enabling higher functionality and performance.
• The multi-layered structure provides efficient routing of electrical signals, reducing signal interference and improving overall performance.

Problems solved by this technology:

• Traditional packaging methods often limit the integration of multiple dies, leading to larger and less efficient devices.
• The formation of vias through the dielectric material allows for better connectivity between the different layers, improving overall functionality.
• The use of redistribution layers with embedded metal layers provides a compact and efficient solution for routing electrical signals.

Benefits of this technology:

• The method allows for the creation of smaller and more compact electronic devices, saving space and reducing manufacturing costs.
• The multi-layered structure improves signal integrity and reduces noise, resulting in better performance and reliability.
• The integration of multiple dies within a single package enables higher functionality and increased processing power.

Original Abstract Submitted

An embodiment is method including forming a first die package over a carrier substrate, the first die package comprising a first die, forming a first redistribution layer over and coupled to the first die, the first redistribution layer including one or more metal layers disposed in one or more dielectric layers, adhering a second die over the redistribution layer, laminating a first dielectric material over the second die and the first redistribution layer, forming first vias through the first dielectric material to the second die and forming second vias through the first dielectric material to the first redistribution layer, and forming a second redistribution layer over the first dielectric material and over and coupled to the first vias and the second vias.