17651347. Dual Damascene Structure in Forming Source/Drain Contacts simplified abstract (Taiwan Semiconductor Manufacturing Co., Ltd.)

Dual Damascene Structure in Forming Source/Drain Contacts

Organization Name

Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor(s)

Chien-Han Chen of Nantou County (TW)

Shih-Yu Chang of Yunlin County (TW)

Chien-Chih Chiu of Xinying City (TW)

Huang-Ming Chen of Hsinchu (TW)

Jyu-Horng Shieh of Hsinchu (TW)

Dual Damascene Structure in Forming Source/Drain Contacts - A simplified explanation of the abstract

This abstract first appeared for US patent application 17651347 titled 'Dual Damascene Structure in Forming Source/Drain Contacts

Simplified Explanation

The patent application describes a method for forming a transistor and connecting it to a metal line and a via. Here are the key points:

• The method starts by forming a transistor with a source/drain region and a gate electrode.
• A source/drain contact plug is then formed and electrically connected to the source/drain region.
• A first inter-layer dielectric is formed over the source/drain contact plug.
• An etch stop layer is formed over the first inter-layer dielectric.
• The etch stop layer is etched to create a via opening.
• A second inter-layer dielectric is formed over the first inter-layer dielectric.
• An etching process is performed to etch the second inter-layer dielectric and extend the via opening into the first inter-layer dielectric, revealing the source/drain contact plug.
• The trench and via opening are then filled in a common process to form a metal line and a via, respectively.

Potential applications of this technology:

• Semiconductor manufacturing
• Integrated circuit fabrication

Problems solved by this technology:

• Efficiently connecting a transistor to a metal line and a via
• Simplifying the process of forming a transistor and connecting it to other components

Benefits of this technology:

• Improved efficiency in semiconductor manufacturing
• Simplified fabrication process for integrated circuits

Original Abstract Submitted

A method includes forming a transistor comprising a source/drain region and a gate electrode, forming a source/drain contact plug over and electrically connecting to the source/drain region, forming a first inter-layer dielectric over the source/drain contact plug, forming an etch stop layer over the first inter-layer dielectric, etching the etch stop layer to form a first via opening, forming a second inter-layer dielectric over the first inter-layer dielectric, performing an etching process, so that the second inter-layer dielectric is etched to form a trench, and the first via opening in the etch stop layer is extended into the first inter-layer dielectric to reveal the source/drain contact plug, and filling the trench and the first via opening in common processes to form a metal line and a via, respectively.