Intel Corporation patent applications published on December 28th, 2023

Patent applications for Intel Corporation on December 28th, 2023

LIQUID METAL (LM) DISPENSING APPARATUS AND METHODS FOR DESIGN AND OPERATION OF SAME (17851968)

Main Inventor

Sangeon Lee

ROAD SURFACE FRICTION BASED PREDICTIVE DRIVING FOR COMPUTER ASSISTED OR AUTONOMOUS DRIVING VEHICLES (18242869)

Main Inventor

Yoshifumi Nishi

TECHNOLOGIES FOR EXPANDED BEAM OPTICAL CONNECTOR (17849557)

Main Inventor

Wesley B. Morgan

AUTOMATICALLY OPEN LAPTOP HINGE (18036823)

Main Inventor

Chunlin BAI

PROCESSOR POWER MANAGEMENT (18339827)

Main Inventor

Altug Koker

DEVICE, METHOD AND SYSTEM FOR TRANSPARENTLY CHANGING A FREQUENCY OF AN INTERCONNECT FABRIC (18244748)

Main Inventor

Chen Ranel

PERFORMING DISTRIBUTED PROCESSING USING DISTRIBUTED MEMORY (17850090)

Main Inventor

Abhishek Anil Sharma

SYSTEMS, APPARATUSES, AND METHODS FOR ADDITION OF PARTIAL PRODUCTS (18456699)

Main Inventor

Robert Valentine

RECONFIGURABLE VECTOR PROCESSING IN A MEMORY (17850044)

Main Inventor

Abhishek Anil Sharma

IMPLICIT MEMORY CORRUPTION DETECTION FOR CONDITIONAL DATA TYPES (17848142)

Main Inventor

David M. Durham

AUTOMATIC FUSION OF ARITHMETIC IN-FLIGHT INSTRUCTIONS (17848284)

Main Inventor

Kristof Du Bois

METHODS AND APPARATUS TO INSERT PROFILING INSTRUCTIONS INTO A GRAPHICS PROCESSING UNIT KERNEL (18463142)

Main Inventor

Konstantin Levit-Gurevich

DATA LOCALITY ENHANCEMENT FOR GRAPHICS PROCESSING UNITS (18339454)

Main Inventor

Christopher J. HUGHES

METHODS AND APPARATUS TO PERFORM CLOUD-BASED ARTIFICIAL INTELLIGENCE OVERCLOCKING (18241062)

Main Inventor

Xia Zhu

SYSTEMS, METHODS, AND APPARATUSES FOR HETEROGENEOUS COMPUTING (18207870)

Main Inventor

Rajesh M. SANKARAN

TECHNOLOGIES FOR PROVIDING EFFICIENT POOLING FOR A HYPER CONVERGED INFRASTRUCTURE (18219557)

Main Inventor

Mohan J. Kumar

HIERARCHICAL CORE VALID TRACKER FOR CACHE COHERENCY (17852189)

Main Inventor

Yedidya Hilewitz

SELECTIVE PROVISIONING OF SUPPLEMENTARY MICRO-OPERATION CACHE RESOURCES (17846688)

Main Inventor

Niranjan Soundararajan

UNIFIED ADDRESS TRANSLATION FOR VIRTUALIZATION OF INPUT/OUTPUT DEVICES (18321490)

Main Inventor

Utkarsh Y. Kakaiya

DEVICE, SYSTEM, AND METHOD FOR INSPECTING DIRECT MEMORY ACCESS REQUESTS (18035705)

Main Inventor

Kaijie Guo

MULTICORE SYNCHRONIZATION MECHANISM FOR TIME CRITICAL RADIO SYSTEMS (17851739)

Main Inventor

Kevin Kinney

CONTROL FLOW INTEGRITY TO PREVENT POTENTIAL LEAKAGE OF SENSITIVE DATA TO ADVERSARIES (17849351)

Main Inventor

Scott D. Constable

EFFICIENT CONVOLUTION IN MACHINE LEARNING ENVIRONMENTS (18322988)

Main Inventor

Dhawal Srivastava

METHOD AND SYSTEM OF IMAGE PROCESSING WITH INCREASED SUBJECTIVE QUALITY 3D RECONSTRUCTION (18030025)

Main Inventor

Zhengxu Huang

METHODS AND APPARATUS FOR ASSISTED DATA REVIEW FOR ACTIVE LEARNING CYCLES (18457169)

Main Inventor

Vinnam Kim

SPUTTER TARGETS AND SOURCES FOR SELF-DOPED SOURCE AND DRAIN CONTACTS (17847625)

Main Inventor

Ilya V. Karpov

MULTI-PATHWAY ROUTING VIA THROUGH HOLE (17851999)

Main Inventor

Suddhasattwa Nad

ORGANIC ADHESION PROMOTOR FOR DIELECTRIC ADHESION TO A COPPER TRACE (17848615)

Main Inventor

Yi YANG

TECHNOLOGIES FOR ISOLATED HEAT DISSIPATING DEVICES (18034133)

Main Inventor

Prabhakar SUBRAHMANYAM

ELECTRICALLY CONDUCTIVE STRIPS ON A SIDE OF A MEMORY MODULE (17848607)

Main Inventor

Min Suet LIM

COPPER RINGS FOR BGA COUNT REDUCTION IN SMALL FORM FACTOR PACKAGES (17849352)

Main Inventor

Kavitha NAGARAJAN

SINGLE LITHOGRAPHY METHODS FOR INTERCONNECT ARCHITECTURES (17846303)

Main Inventor

Yi Yang

PACKAGING ARCHITECTURE WITH ROUNDED TRACES FOR ON-PACKAGE HIGH-SPEED INTERCONNECTS (17847282)

Main Inventor

Cemil Geyik

SINX ADHESION PROMOTER WITH ADHESION HOLE FEATURES IN PACKAGING SUBSTRATE FOR RELIABILITY PERFORMANCE ENHANCEMENT (17852039)

Main Inventor

Jieying KONG

HYPER DENSITY PACKAGE SUBSTRATE AND MEMORY COUPLED TO A MODIFIED SEMI-ADDITIVE PROCESS BOARD (17848630)

Main Inventor

Kavitha NAGARAJAN

ASYMMETRICAL DIELECTRIC-TO-METAL ADHESION ARCHITECTURE FOR ELECTRONIC PACKAGES (17848053)

Main Inventor

Suddhasattwa Nad

ELECTRICAL CONDUCTOR EXTENDING FROM A SURFACE OF A SUBSTRATE (17848643)

Main Inventor

Telesphor KAMGAING

SILICON NITRIDE LAYER UNDER A COPPER PAD (17848624)

Main Inventor

Brandon C. MARIN

INTEGRATED CIRCUIT PACKAGES WITH SILVER AND SILICON NITRIDE MULTI-LAYER (17851957)

Main Inventor

Cemil S. Geyik

INTEGRATED CIRCUIT STRUCTURE WITH RECESSED SELF-ALIGNED DEEP BOUNDARY VIA (17850779)

Main Inventor

Mohit HARAN

SELECTIVE BOTTOMLESS GRAPHENE LINED INTERCONNECTS (17852028)

Main Inventor

Nita CHANDRASEKHAR

INTEGRATED CIRCUIT DEVICES WITH ANGLED TRANSISTORS AND ANGLED ROUTING TRACKS (18314875)

Main Inventor

Sagar Suthram

MICROELECTRONIC DIE WITH TWO DIMENSIONAL (2D) COMPLEMENTARY METAL OXIDE SEMICONDUCTOR DEVICES IN AN INTERCONNECT STACK THEREOF (17849207)

Main Inventor

Kevin P. O'Brien

Brief explanation

The patent application describes a microelectronic device and a method of making it, which includes a semiconductor package and an IC device assembly. The device consists of a substrate, a front end of line (FEOL) stack with multiple transistors, and a back end of line (BEOL) stack with multiple transistors made of a transition metal dichalcogenide (TMD) material. The second transistors in the BEOL stack are used for voltage regulation to control the power supply to the device.

• The device includes a substrate, a FEOL stack, and a BEOL stack.
• The FEOL stack contains multiple transistors.
• The BEOL stack contains multiple transistors made of a TMD material.
• The TMD transistors in the BEOL stack are used for voltage regulation.
• The device is part of a semiconductor package and an IC device assembly.
• The method of making the device is also described in the patent application.

Potential applications of this technology:

• Microelectronics industry
• Semiconductor manufacturing
• Integrated circuit design and production

Problems solved by this technology:

• Efficient voltage regulation in microelectronic devices
• Improved power supply control in semiconductor packages

Benefits of this technology:

• Enhanced performance and reliability of microelectronic devices
• More efficient power management in IC device assemblies
• Potential for advancements in semiconductor manufacturing processes.

Abstract

A microelectronic device, a semiconductor package including the device, an IC device assembly including the package, and a method of making the device. The device includes a substrate; a first structure on the substrate, the first structure corresponding to a front end of line (FEOL) stack of the device and including a plurality of first transistors therein; and a second structure on the substrate, the second structure corresponding to a back end of line (BEOL) stack of the device, and including a plurality of second transistors therein, the plurality of second transistors including a transition metal dichalcogenide (TMD) material. The second transistors are part of a voltage regulation architecture to regulate voltage supply to the die.

INTEGRATED CIRCUIT STRUCTURES HAVING MEMORY WITH BACKSIDE POWER DELIVERY (17851985)

Main Inventor

Abhishek Anil SHARMA

Brief explanation

The patent application describes structures with memory and backside power delivery. The integrated circuit structure includes a front-side structure with nanowire-based transistors and metallization layers. One of the metal layers has an array of uninterrupted signal lines. The backside structure includes a ground metal line.

• The integrated circuit structure includes nanowire-based transistors and metallization layers.
• One of the metal layers has an array of uninterrupted signal lines.
• The backside structure includes a ground metal line.

Potential Applications

This technology has potential applications in various fields, including:

• Electronics manufacturing
• Semiconductor industry
• Memory devices
• Integrated circuits

Problems Solved

The technology addresses the following problems:

• Efficient power delivery in integrated circuits
• Signal line interruptions in metal layers
• Grounding issues in backside structures

Benefits

The technology offers the following benefits:

• Improved power delivery efficiency
• Uninterrupted signal lines for better performance
• Enhanced grounding capabilities in backside structures

Abstract

Structures having memory with backside power delivery are described. In an example, an integrated circuit structure includes a front-side structure including a device layer having a plurality of nanowire-based transistors, and a plurality of metallization layers above the nanowire-based transistors of the device layer. One of the metal layers includes an array of uninterrupted signal lines. A backside structure is below the nanowire-based transistors of the device layer. The backside structure includes a ground metal line.

MICROELECTRONIC ASSEMBLIES WITH ANCHOR LAYER AROUND A BRIDGE DIE (17848069)

Main Inventor

Benjamin T. Duong

Brief explanation

The patent application describes microelectronic assemblies and methods for their fabrication. Here are the key points:

• The microelectronic assembly includes a substrate with a cavity, a first die nested in the cavity, and a liner layer on the substrate and around the first die.
• The liner layer is made of silicon or aluminum, and may contain nitrogen, oxygen, and carbon.
• A second layer is formed on the liner layer and extends into the cavity, and a second die is placed on the second layer.
• The conductive contacts on the first die are electrically coupled to the second die through conductive vias in the second layer and the liner layer.

Potential applications of this technology:

• Microelectronics manufacturing
• Semiconductor packaging
• Integrated circuit fabrication

Problems solved by this technology:

• Provides a protective liner layer for the first die and the cavity, preventing damage and improving reliability.
• Enables electrical coupling between the first and second dies through conductive vias, facilitating communication and data transfer.

Benefits of this technology:

• Enhanced reliability and durability of microelectronic assemblies
• Improved electrical connectivity between different components
• Enables miniaturization and integration of multiple dies in a single assembly.

Abstract

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first layer of a substrate having a cavity; a first die at least partially nested in the cavity in the first layer of the substrate, the first die having a surface with conductive contacts; a liner layer on the first layer, in a portion of the cavity, and on and around the first die, wherein a material of the liner layer includes: silicon or aluminum, and one or more of nitrogen, oxygen, and carbon; a second layer on the liner layer, wherein the second layer extends into the cavity and is on and around the first die; and a second die on the second layer, wherein the second die is electrically coupled to the conductive contacts on the first die by conductive vias through the second layer and the liner layer.

INORGANIC-BASED EMBEDDED-DIE LAYERS FOR MODULAR SEMICONDUCTIVE DEVICES (18367285)

Main Inventor

Srinivas V. PIETAMBARAM

Brief explanation

==Abstract==

A glass substrate is used to house a multi-die interconnect bridge in a semiconductor device package. Through-glass vias are used to connect the bridge to a surface for mounting on a semiconductor package substrate.

Patent/Innovation Explanation

• Glass substrate is used as a housing for a multi-die interconnect bridge in a semiconductor device package.
• Through-glass vias are used to establish communication between the bridge and a surface for mounting on a semiconductor package substrate.

Potential Applications

This technology has potential applications in the semiconductor industry, specifically in the development of semiconductor device packages. It can be used in various electronic devices, such as smartphones, computers, and other consumer electronics.

Problems Solved

• Provides a solution for housing a multi-die interconnect bridge in a semiconductor device package.
• Enables communication between the bridge and a surface for mounting on a semiconductor package substrate.

Benefits

• Utilizing a glass substrate as a housing can provide improved durability and thermal stability for the semiconductor device package.
• Through-glass vias enable efficient communication between the bridge and the semiconductor package substrate, enhancing overall performance and functionality.

Abstract

A glass substrate houses an embedded multi-die interconnect bridge that is part of a semiconductor device package. Through-glass vias communicate to a surface for mounting on a semiconductor package substrate.

MICROELECTRONIC STRUCTURES INCLUDING BRIDGES (18462600)

Main Inventor

Omkar G. Karhade

Brief explanation

The patent application describes microelectronic structures with bridges and related methods. Here is a simplified explanation of the abstract:

• The microelectronic structure includes a substrate with two metal layers and a cavity in the substrate.
• The first and second metal layers are partially exposed in the cavity, with the first metal layer overlapping the second metal layer.
• A bridge component is present in the cavity, with a conductive contact on each face.
• The second face of the bridge component is towards the bottom surface of the cavity, and the first metal layer is between the second face and the second metal layer.
• The second conductive contact is electrically connected to the second metal layer in the cavity.

Potential applications of this technology:

• Microelectronics manufacturing
• Integrated circuits
• Semiconductor devices

Problems solved by this technology:

• Provides a structure for connecting different metal layers in a microelectronic device.
• Allows for electrical connections between metal layers in a cavity.

Benefits of this technology:

• Enables efficient and reliable electrical connections in microelectronic structures.
• Provides a compact and space-saving design for connecting metal layers.
• Enhances the performance and functionality of microelectronic devices.

Abstract

Disclosed herein are microelectronic structures including bridges, and related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate with first and second metal layers; a cavity in the substrate, where a portion of the first and second metal layers, are exposed with the portion of the first metal layer partially overlapping the portion of the second metal layer; and a bridge component in the cavity, having a first conductive contact at a first face and a second conductive contact at a second face opposing the first face, the second face towards a bottom surface of the cavity, the portion of the first metal layer is between the second face of the bridge component and the portion of the second metal layer, and the second conductive contact is electrically coupled to the portion of the second metal layer in the cavity.

PACKAGING ARCHITECTURE WITH TRENCH VIA ROUTING FOR ON-PACKAGE HIGH-SPEED INTERCONNECTS (17847257)

Main Inventor

Cemil Geyik

Brief explanation

The patent application describes a microelectronic assembly that includes a package substrate and an integrated circuit (IC) die. The package substrate has a conductive trace surrounded by a conductive structure coupled to a ground connection. The substrate also has alternating layers of metallization and dielectric material. The IC die is connected to the conductive trace through a conductive pathway.

• The microelectronic assembly includes a package substrate with a conductive trace and a conductive structure coupled to a ground connection.
• The package substrate has alternating layers of metallization and dielectric material.
• The IC die is connected to the conductive trace through a conductive pathway.
• The conductive trace includes a trench via in one of the dielectric layers.
• The conductive structure includes grounded plates that extend across the length and width of the package substrate in metallization layers on either side of the dielectric layer.

Potential Applications:

• Microelectronic devices and systems
• Integrated circuits
• Electronic packaging

Problems Solved:

• Provides a conductive pathway for connecting an IC die to a package substrate
• Ensures proper grounding of the conductive trace
• Improves the performance and reliability of microelectronic assemblies

Benefits:

• Enhanced electrical connectivity
• Improved signal integrity
• Increased reliability and performance of microelectronic assemblies

Abstract

Embodiments of a microelectronic assembly comprise: a package substrate comprising a conductive trace in a dielectric material, the conductive trace surrounded by a conductive structure coupled to a ground connection, the package substrate further comprising metallization layers alternating with dielectric layers of the dielectric material; and an integrated circuit (IC) die coupled to a surface of the package substrate, the IC die being coupled to the conductive trace by a conductive pathway. The dielectric layers and the metallization layers are parallel to the surface of the package substrate, the conductive trace comprises a trench via in one of the dielectric layers, and the conductive structure comprises grounded plates extending across a length and width of the package substrate in metallization layers on either side of the dielectric layer.

PACKAGING ARCHITECTURE WITH CAVITIES FOR EMBEDDED INTERCONNECT BRIDGES (17847407)

Main Inventor

Sameer Paital

Brief explanation

The patent application describes a microelectronic assembly that includes an interposer, integrated circuit (IC) dies, and a bridge die. The interposer is made of a dielectric material and has a pad of conductive material with a ceramic liner and fin structures. The IC dies are connected to the interposer, and the bridge die is conductively coupled to the IC dies. The bridge die has a first face near the IC dies and a second face in contact with the pad.

• The microelectronic assembly includes an interposer made of a dielectric material.
• The interposer has a pad of conductive material with a ceramic liner and fin structures.
• At least two IC dies are connected to the interposer.
• A bridge die is conductively coupled to the IC dies.
• The bridge die has a first face near the IC dies and a second face in contact with the pad.

Potential Applications

• Microelectronic devices and systems
• Semiconductor industry
• Electronics manufacturing

Problems Solved

• Improved electrical connectivity between IC dies and the interposer
• Enhanced thermal management through the use of ceramic liner and fin structures
• Increased reliability and performance of microelectronic assemblies

Benefits

• Higher efficiency and functionality of microelectronic devices
• Improved heat dissipation and thermal stability
• Enhanced electrical performance and signal integrity

Abstract

Embodiments of a microelectronic assembly comprise an interposer comprising a dielectric material and a pad of conductive material having at least one of a ceramic liner and fin structures; at least two integrated circuit (IC) dies coupled to the interposer; and a bridge die in the interposer conductively coupled to the at least two IC dies. The bridge die has a first face and an opposing second face, the first face of the bridge die is proximate to the at least two IC dies, and the second face of the bridge die is in contact with the pad.

INTEGRATED CIRCUIT PACKAGE WITH PSEUDO-STRIPLINE ARCHITECTURE (17848059)

Main Inventor

Eng Huat Goh

Brief explanation

The abstract describes a patent application for a method of routing IC device packages using a pseudo-stripline architecture. This architecture includes a separate routing structure that helps create a stripline structure within the package substrate, resulting in improved EMI performance.

• The patent application proposes a method of routing IC device packages using a pseudo-stripline architecture.
• The stripline structure is created, in part, by a routing structure separate from the package substrate's routing.
• A metallization feature within the redistribution layer (RDL) of the routing structure helps shield the signal route within the top metallization level of the package substrate.
• This method allows for fewer levels of metallization, reduced thickness, and lower cost for the package substrate.
• Despite these cost-saving measures, the IC device package still offers excellent EMI performance.

Potential Applications

This technology can be applied in various industries and applications, including:

• Electronics manufacturing
• Semiconductor packaging
• Integrated circuit design
• Telecommunications
• Consumer electronics

Problems Solved

The patent application addresses the following problems:

• Electromagnetic interference (EMI) in IC device packages
• Cost and complexity associated with multiple levels of metallization in package substrates
• Limited options for reducing package substrate thickness without compromising EMI performance

Benefits

The proposed technology offers several benefits:

• Improved EMI performance in IC device packages
• Reduced cost and complexity by using fewer levels of metallization in the package substrate
• Thinner package substrates without sacrificing EMI performance
• Enhanced signal integrity and reliability in IC chip routing

Abstract

IC device package routing with metallization features comprising a pseudo-stripline architecture in which the stripline structure is provisioned, in part, by a routing structure separate from routing within the package substrate. A signal route within top metallization level of a package substrate may be electrically shielded, in part, with a metallization feature within a redistribution layer (RDL) of a routing structure that couples one or more IC chips to the package substrate. Accordingly, a package substrate may have fewer levels of metallization, reduced thickness, and/or lower cost while the IC device package still offers excellent EMI performance.

TECHNOLOGIES FOR OVERLAY METROLOGY MARKS (17847111)

Main Inventor

Martin N. Weiss

Brief explanation

The patent application describes techniques for creating overlay metrology marks on semiconductor wafers. These marks consist of a series of grating lines on different layers of the wafer. When viewed from above, the marks create a moire pattern that changes as the positions of the marks shift. 

• The overlay metrology marks are formed on different layers of a semiconductor wafer.
• The marks are made up of grating lines that create a moire pattern when viewed from above.
• The moire pattern changes as the positions of the marks move.
• At least one of the marks has non-uniform grating line spacing, allowing for a wider range of overlay errors to be detected.

Potential Applications

• Semiconductor manufacturing
• Metrology and alignment in the semiconductor industry

Problems Solved

• Accurate measurement and alignment of different layers in semiconductor wafers
• Detection of overlay errors in semiconductor manufacturing

Benefits

• Improved accuracy in measuring and aligning different layers of semiconductor wafers
• Ability to detect a wider range of overlay errors in manufacturing processes

Abstract

Techniques for forming overlay metrology marks are disclosed. In the illustrative embodiment, a first overlay metrology mark is on a first layer of a semiconductor wafer, and a second metrology mark is formed on a second layer above the first layer. The overlay metrology marks are embodied as a series of grating lines. Looking downward at the overlay metrology marks, the two metrology marks form a moire pattern, with the light and dark regions of the moire pattern moving as the relative positions of the overlay metrology marks move. In the illustrative embodiment, at least one of the overlay metrology marks has non-uniform grating line spacing. As a result, the moire pattern is not identical if the overlay metrology mark is shifted by one grating line, allowing for a wider range of overlay errors to be detected.

SLOTTED STIFFENER FOR A PACKAGE SUBSTRATE (17848639)

Main Inventor

Kavitha NAGARAJAN

Brief explanation

The abstract describes a patent application related to a stiffener for a semiconductor package surface. The stiffener includes slots that allow a gasket to be placed over it, enabling electrical coupling with the ground or VSS of the semiconductor package. The gasket is made of a material that can block or absorb electromagnetic interference (EMI) or radio frequency interference (RFI). 

• The patent application is for a stiffener designed for a semiconductor package surface.
• The stiffener includes slots that allow a gasket to be placed over it.
• The gasket is used to electrically couple with the ground or VSS of the semiconductor package.
• The gasket is made of a material that can block or absorb EMI or RFI.
• The invention aims to provide improved electrical coupling and EMI/RFI protection for semiconductor packages.

Potential Applications

• Semiconductor packaging industry
• Electronics manufacturing industry
• Telecommunications industry
• Aerospace industry

Problems Solved

• Inadequate electrical coupling between the stiffener and the ground/VSS of a semiconductor package.
• Insufficient protection against EMI or RFI interference in semiconductor packages.

Benefits

• Enhanced electrical coupling between the stiffener and the ground/VSS of a semiconductor package.
• Improved protection against EMI or RFI interference in semiconductor packages.
• Potential reduction in signal interference and improved performance of electronic devices.

Abstract

Embodiments herein relate to systems, apparatuses, or processes directed to a stiffener for a surface of a semiconductor package, where the stiffener includes slots that allow a gasket to go over the stiffener to electrically couple with a ground or a VSS of the semiconductor package. In embodiments, the gasket may include a material that blocks or absorbs EMI or RFI. Other embodiments may be described and/or claimed.

STRESS-REDUCING DIELECTRIC-TO-METAL ADHESION ARCHITECTURE FOR ELECTRONIC PACKAGES (17847652)

Main Inventor

Yi Yang

Brief explanation

The abstract describes an electronic device package that includes multiple layers of different materials to enhance its functionality and performance.

• The package substrate has a conductive feature that connects to an integrated circuit die.
• The first dielectric layer, made of silicon and nitrogen, is applied over the conductive feature.
• A second dielectric layer, also made of silicon and nitrogen, is added on top of the first layer with a different thickness.
• Finally, a third dielectric layer made of an organic material is applied over the second layer.

Potential applications of this technology:

• Electronic devices such as smartphones, tablets, and computers.
• Integrated circuits and microchips used in various industries.

Problems solved by this technology:

• Enhances the conductivity and performance of the electronic device package.
• Provides better insulation and protection for the integrated circuit die.

Benefits of this technology:

• Improved functionality and performance of electronic devices.
• Enhanced durability and protection for integrated circuits.
• Increased efficiency and reliability of electronic device packages.

Abstract

An electronic device package comprises a conductive feature over a first surface of a package substrate, the conductive feature to couple to an integrated circuit die; a first dielectric layer on the conductive feature, the first dielectric layer having a first thickness and comprising silicon and nitrogen; a second dielectric layer over the first dielectric layer and having a second thickness different than the first thickness and comprising silicon and nitrogen; and a third dielectric layer over the second dielectric layer and comprising an organic material.

DEVICE-TO-DEVICE COMMUNICATION SYSTEM, PACKAGES, AND PACKAGE SYSTEM (18253954)

Main Inventor

Tolga ACIKALIN

Brief explanation

The patent application describes a device-to-device communication system that includes two devices, each consisting of an antenna, a radio frequency front-end circuit, and a baseband circuit. These devices can be in the form of chiplets or packages. The system also includes a cover structure that houses both devices and a radio frequency signal interface that wirelessly connects them.

• The system includes two devices with antennas, circuits, and baseband circuits.
• The devices can be chiplets or packages.
• A cover structure houses both devices.
• A radio frequency signal interface wirelessly connects the devices.

Potential Applications

• Wireless communication between devices in close proximity.
• Internet of Things (IoT) devices communicating with each other.
• Device-to-device data transfer in smart homes or offices.

Problems Solved

• Enables direct communication between devices without the need for a centralized network.
• Provides a compact and efficient solution for device-to-device communication.
• Reduces the complexity and cost of implementing wireless communication between devices.

Benefits

• Faster and more efficient communication between devices.
• Simplifies the setup and configuration of device-to-device communication.
• Enables seamless integration of devices in various environments.

Abstract

In various aspects, a device-to-device communication system is provided including a first device and a second device. Each of the first device and the second device includes an antenna, a radio frequency frond-end circuit, and a baseband circuit. Each of the first device and the second device are at least one of a chiplet or a package. The device-to-device communication system further includes a cover structure housing the first device and the second device. Each of the first device and the second device are at least one of a chiplet or a package. The device-to-device communication system further includes a radio frequency signal interface wirelessly communicatively coupling the first device and the second device. The radio frequency signal interface includes the first antenna and the second antenna.

PACKAGED SEMICONDUCTOR DIE WITH BUMPLESS DIE-PACKAGE INTERFACE FOR BUMPLESS BUILD-UP LAYER (BBUL) PACKAGES (18244689)

Main Inventor

Pramod MALATKAR

Brief explanation

The abstract describes a semiconductor package with a bumpless die-package interface and methods of fabrication. The package includes a substrate with a lowermost layer of conductive vias and a semiconductor die embedded in the substrate. The die has an uppermost layer of conductive lines, one of which is directly connected to a conductive via of the substrate.

• The semiconductor package has a bumpless die-package interface.
• The package includes a substrate with a lowermost layer of conductive vias.
• A semiconductor die is embedded in the substrate.
• The die has an uppermost layer of conductive lines.
• One of the conductive lines is directly connected to a conductive via of the substrate.

Potential Applications

• Semiconductor packaging industry
• Electronics manufacturing industry

Problems Solved

• Simplifies the die-package interface
• Improves the connectivity between the die and the substrate

Benefits

• Enhanced performance and reliability of semiconductor packages
• Streamlined fabrication process
• Cost-effective solution for semiconductor packaging

Abstract

A packaged semiconductor die with a bumpless die-package interface and methods of fabrication are described. For example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines, one of which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate. In another example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines with a layer of conductive vias disposed thereon. At least one of the conductive lines is coupled directly to a conductive via of the semiconductor die which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate.

PACKAGE ARCHITECTURE WITH VERTICAL STACKING OF INTEGRATED CIRCUIT DIES HAVING PLANARIZED EDGES (17846086)

Main Inventor

Sagar Suthram

Brief explanation

The abstract describes embodiments of an integrated circuit (IC) die that consist of two regions: a first region and a second region. The first region has two surfaces, with one surface perpendicular to the other. The second region is attached to the first region along a planar interface that is perpendicular to the first surface and parallel to the second surface. The second region has a surface that is coplanar with the first surface. 

• The first region of the IC die is made of a dielectric material.
• The first region contains layers of conductive traces embedded in the dielectric material. Each layer of conductive traces is parallel to the second surface, and the traces are perpendicular to the first surface.
• The first region also includes conductive vias that pass through the dielectric material.
• The first surface of the first region has bond-pads, which are exposed portions of the conductive traces.
• The second region of the IC die is made of a material different from the dielectric material.

Potential Applications

• Integrated circuits and microchips
• Electronic devices and gadgets
• Communication systems and networks

Problems Solved

• Provides a structure for integrating different materials in an IC die
• Enables efficient routing of conductive traces in the dielectric material
• Facilitates the connection of external devices to the IC die through bond-pads

Benefits

• Enhanced performance and functionality of integrated circuits
• Improved reliability and durability of IC dies
• Enables miniaturization and compactness of electronic devices

Abstract

Embodiments of an integrated circuit (IC) die comprise: a first region having a first surface and a second surface, the first surface being orthogonal to the second surface; and a second region attached to the first region along a planar interface that is orthogonal to the first surface and parallel to the second surface, the second region having a third surface coplanar with the first surface. The first region comprises: a dielectric material; layers of conductive traces in the dielectric material, each layer of the conductive traces being parallel to the second surface such that the conductive traces are orthogonal to the first surface; conductive vias through the dielectric material; and bond-pads on the first surface, the bond-pads comprising portions of the conductive traces exposed on the first surface, and the second region comprises a material different from the dielectric material.

PACKAGE ARCHITECTURE WITH VERTICALLY STACKED BRIDGE DIES HAVING PLANARIZED EDGES (17846129)

Main Inventor

Sagar Suthram

Brief explanation

The abstract describes embodiments of an integrated circuit (IC) die that consists of multiple IC dies connected through interconnects. The interconnects are located on the first surface of the first IC die and the second surfaces of the second IC dies, allowing for contact between the two surfaces. The interconnects are made up of dielectric-dielectric bonds and metal-metal bonds, with first bond-pads in the first IC die and second bond-pads in the second IC dies. The first IC die includes a substrate attached to a metallization stack, which is a series of conductive traces in a dielectric material. The first bond-pads are exposed portions of the conductive traces on the first surface.

• The patent application describes an integrated circuit die that connects multiple IC dies through interconnects.
• The interconnects are located on the first surface of the first IC die and the second surfaces of the second IC dies.
• The interconnects consist of dielectric-dielectric bonds and metal-metal bonds.
• The first IC die includes a substrate and a metallization stack, which is a series of conductive traces in a dielectric material.
• The first bond-pads are exposed portions of the conductive traces on the first surface.

Potential Applications

This technology has potential applications in various fields, including:

• Electronics manufacturing
• Semiconductor industry
• Integrated circuit design

Problems Solved

This technology addresses the following problems:

• Efficiently connecting multiple IC dies in an integrated circuit
• Ensuring reliable and robust interconnects between IC dies
• Facilitating communication and data transfer between IC dies

Benefits

The benefits of this technology include:

• Improved integration and connectivity of IC dies
• Enhanced performance and functionality of integrated circuits
• Increased reliability and durability of interconnects

Abstract

Embodiments of an integrated circuit (IC) die comprise: a first IC die coupled to at least two second IC dies by interconnects on a first surface of the first IC die and second surfaces of the second IC dies such that the first surface is in contact with the second surfaces. The second surfaces are coplanar, the interconnects comprise dielectric-dielectric bonds and metal-metal bonds, the metal-metal bonds include first bond-pads in the first IC die and second bond-pads in the second IC dies, the first IC die comprises a substrate attached to a metallization stack along a planar interface that is orthogonal to the first surface, the metallization stack comprises a plurality of layers of conductive traces in a dielectric material, and the first bond-pads comprise portions of the conductive traces exposed on the first surface.

PACKAGE ARCHITECTURE OF THREE-DIMENSIONAL INTERCONNECT CUBE WITH INTEGRATED CIRCUIT DIES HAVING PLANARIZED EDGES (17846153)

Main Inventor

Sagar Suthram

Brief explanation

The abstract describes embodiments of an integrated circuit (IC) die that includes a metallization stack and a substrate. The metallization stack consists of a dielectric material, multiple layers of conductive traces, and conductive vias. The substrate is attached to the metallization stack along a planar interface. The metallization stack also includes bond-pads on different surfaces.

• The IC die includes a metallization stack with conductive traces and vias, and a substrate.
• The metallization stack is made up of a dielectric material and multiple layers of conductive traces.
• The substrate is attached to the metallization stack along a planar interface.
• The metallization stack has bond-pads on different surfaces, including the first, second, third, fourth, and fifth surfaces.
• The first surface is parallel to the planar interface, while the second and third surfaces are parallel to each other and orthogonal to the first surface.
• The fourth and fifth surfaces are parallel to each other and orthogonal to both the first and second surfaces.

Potential applications of this technology:

• Integrated circuits and microchips
• Electronic devices and systems
• Semiconductor manufacturing

Problems solved by this technology:

• Efficient integration of conductive traces and vias in an IC die
• Improved connectivity and signal transmission within the IC die

Benefits of this technology:

• Enhanced performance and functionality of integrated circuits
• Increased reliability and durability of electronic devices
• Simplified manufacturing processes for semiconductor devices

Abstract

Embodiments of an integrated circuit (IC) die comprise: a metallization stack including a dielectric material, a plurality of layers of conductive traces in the dielectric material and conductive vias through the dielectric material; and a substrate attached to the metallization stack along a planar interface. The metallization stack comprises bond-pads on a first surface, a second surface, a third surface, a fourth surface, and a fifth surface. The first surface is parallel to the planar interface between the metallization stack and the substrate, the second surface is parallel to the third surface and orthogonal to the first surface, and the fourth surface is parallel to the fifth surface and orthogonal to the first surface and the second surface.

PACKAGING ARCHITECTURE WITH COAXIAL PILLARS FOR HIGH-SPEED INTERCONNECTS (17847434)

Main Inventor

Hiroki Tanaka

Brief explanation

The abstract describes a microelectronic assembly that includes a package substrate, an interposer, and an integrated circuit (IC) die. The interposer is made of a dielectric material and has a conductive pillar and a conductive structure surrounding the pillar. The IC die is connected to the interposer on the opposite side of the package substrate. The conductive pillar provides a conductive connection between the IC die and the package substrate, while the conductive structure is connected to a ground connection.

• The microelectronic assembly includes a package substrate, an interposer, and an IC die.
• The interposer is made of a dielectric material and has a conductive pillar and a conductive structure.
• The conductive pillar provides a conductive connection between the IC die and the package substrate.
• The conductive structure is connected to a ground connection.

Potential Applications

• Microelectronics manufacturing
• Integrated circuit packaging
• Electronic devices and systems

Problems Solved

• Provides a conductive connection between the IC die and the package substrate
• Ensures proper grounding of the conductive structure

Benefits

• Improved performance and reliability of microelectronic assemblies
• Enhanced electrical connectivity and signal transmission
• Efficient grounding mechanism for the conductive structure

Abstract

Embodiments of a microelectronic assembly comprise a microelectronic assembly, comprising: a package substrate; an interposer coupled to the package substrate, the interposer comprising a dielectric material, a conductive pillar) through the dielectric material and a conductive structure at least partially surrounding the conductive pillar, the conductive structure separated from the conductive pillar by the dielectric material; and an integrated circuit (IC) die coupled to the interposer on a side opposite to the package substrate. The conductive pillar conductively couples the IC die to the package substrate, and the conductive structure is coupled to a ground connection.

MICROELECTRONIC ASSEMBLIES INCLUDING SOLDER AND NON-SOLDER INTERCONNECTS (17848246)

Main Inventor

Alois Nitsch

Brief explanation

The abstract describes a patent application for microelectronic assemblies, related devices, and methods. The assembly includes a first die with two surfaces, a redistribution layer (RDL) with a surface, and a second die. The first surface of the first die is electrically connected to the surface of the RDL using non-solder interconnects, while the second die is directly connected to the second surface of the first die using solder interconnects.

• The patent application is for a microelectronic assembly with a specific configuration of interconnects.
• The assembly includes a first die, a redistribution layer (RDL), and a second die.
• The first die has two surfaces, and the first surface is connected to the RDL using non-solder interconnects.
• The second die is directly connected to the second surface of the first die using solder interconnects.

Potential Applications

• Microelectronics manufacturing
• Semiconductor industry
• Electronic devices and systems

Problems Solved

• Improved electrical coupling between different components in a microelectronic assembly
• Enhanced reliability and performance of microelectronic devices
• Efficient use of space in microelectronic assemblies

Benefits

• Higher electrical connectivity and signal transmission efficiency
• Increased reliability and durability of microelectronic devices
• Compact and space-saving design for microelectronic assemblies

Abstract

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface and an opposing second surface; a redistribution layer (RDL) having a surface, wherein the first surface of the first die is on and electrically coupled to the surface of the RDL by non-solder interconnects; and a second die at the second surface of the first die, wherein the second die is electrically coupled directly to the second surface of the first die by solder interconnects.

PACKAGE ARCHITECTURE OF PHOTONIC SYSTEM WITH VERTICALLY STACKED DIES HAVING PLANARIZED EDGES (17846173)

Main Inventor

Sagar Suthram

Brief explanation

The abstract describes embodiments of an integrated circuit (IC) die that consist of multiple regions and interfaces. 

• The first region of the IC die has two surfaces, with the first surface being perpendicular to the second surface.
• The second region is made of semiconductor material and is attached to the first region along a planar interface that is parallel to the second surface and perpendicular to the first surface.
• The third region contains optical structures of a photonic IC and is attached to the second region along a planar interface that is parallel to the first planar interface.
• The first region includes multiple layers of conductive traces in a dielectric material, with each layer being parallel to the second surface and perpendicular to the first surface.
• The first surface of the first region has bond-pads, which are portions of the conductive traces exposed on the surface.

Potential applications of this technology:

• Integrated circuits with improved optical capabilities.
• Photonic integrated circuits with enhanced functionality.
• High-speed data communication and processing applications.
• Optoelectronic devices and systems.

Problems solved by this technology:

• Integration of optical structures into an IC die.
• Efficient coupling of optical and electronic components.
• Enhanced performance and functionality of integrated circuits.

Benefits of this technology:

• Improved data transfer rates and processing speeds.
• Compact and integrated design.
• Higher efficiency and reliability.
• Enables the development of advanced optoelectronic systems.

Abstract

Embodiments of an integrated circuit (IC) die comprise a first region having a first surface and a second surface, the first surface being orthogonal to the second surface; a second region comprising a semiconductor material, the second region attached to the first region along a first planar interface that is orthogonal to the first surface and parallel to the second surface; and a third region comprising optical structures of a photonic IC, the third region attached to the second region along a second planar interface that is parallel to the first planar interface. The first region comprises: a plurality of layers of conductive traces in a dielectric material, each layer of the conductive traces being parallel to the second surface such that the conductive traces are orthogonal to the first surface; and bond-pads on the first surface, the bond-pads comprising portions of respective conductive traces exposed on the first surface.

PACKAGE ARCHITECTURE WITH VERTICAL STACKING OF INTEGRATED CIRCUIT DIES HAVING PLANARIZED EDGES AND MULTI-SIDE ROUTING (17846109)

Main Inventor

Sagar Suthram

Brief explanation

The abstract describes embodiments of an integrated circuit (IC) die that consist of three regions attached to each other. The first region has a surface, the second region is attached to the first region along a planar interface, and the third region is attached to the second region along another planar interface. The third region has a surface that is coplanar with the surface of the first region. The first and third regions contain multiple layers of conductive traces in a dielectric material, and bond-pads on the surfaces expose portions of these conductive traces.

• The IC die consists of three regions attached to each other.
• The first and third regions have surfaces that are coplanar.
• The conductive traces in the first and third regions are orthogonal to the surfaces.
• Bond-pads on the surfaces expose portions of the conductive traces.

Potential Applications

This technology can be applied in various fields that utilize integrated circuits, such as:

• Electronics manufacturing
• Semiconductor industry
• Consumer electronics
• Telecommunications
• Automotive electronics

Problems Solved

The technology addresses the following problems:

• Integration of multiple regions in an IC die
• Ensuring coplanarity of surfaces in different regions
• Efficient routing of conductive traces in a dielectric material
• Providing exposed bond-pads for connectivity

Benefits

The technology offers several benefits:

• Improved integration of different regions in an IC die
• Enhanced coplanarity of surfaces, facilitating manufacturing processes
• Efficient routing of conductive traces, optimizing circuit design
• Exposed bond-pads for easy connectivity during assembly and testing

Abstract

Embodiments of an integrated circuit (IC) die comprise: a first region having a first surface; a second region attached to the first region along a first planar interface that is orthogonal to the first surface; and a third region attached to the second region along a second planar interface that is parallel to the first planar interface, the third region having a second surface, the second surface being coplanar with the first surface. The first region and the third region comprise a plurality of layers of conductive traces in a dielectric material, the conductive traces being orthogonal to the first and second surfaces; and bond-pads on the first and second surfaces, the bond-pads comprising portions of the respective conductive traces exposed on the first and second surfaces.

SIGE:GAB SOURCE OR DRAIN STRUCTURES WITH LOW RESISTIVITY (17850782)

Main Inventor

Debaleena NANDI

Brief explanation

The patent application describes integrated circuit structures with low resistivity source or drain structures. The structures include a fin with a lower and upper portion, and a gate stack over the upper portion. There are two source or drain structures on either side of the gate stack, each embedded in the fin. These structures contain silicon, germanium, gallium, and boron, and have a resistivity less than 2E-9 Ohm cm.

• Integrated circuit structures with low resistivity source or drain structures
• Structures include a fin with a lower and upper portion
• Gate stack is placed over the upper portion of the fin
• Two source or drain structures are embedded in the fin on either side of the gate stack
• Source or drain structures contain silicon, germanium, gallium, and boron
• Resistivity of the structures is less than 2E-9 Ohm cm

Potential Applications

• Semiconductor industry
• Integrated circuit manufacturing
• Electronics manufacturing

Problems Solved

• High resistivity in source or drain structures
• Improved performance and efficiency of integrated circuits

Benefits

• Lower resistivity in source or drain structures
• Enhanced conductivity and performance of integrated circuits
• Improved efficiency and power consumption in electronic devices

Abstract

Integrated circuit structures having source or drain structures with low resistivity are described. In an example, integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. Each epitaxial structure of the first and second source or drain structures include silicon, germanium, gallium and boron. The first and second source or drain structures have a resistivity less than 2E-9 Ohm cm.

LOWER DEVICE ACCESS IN STACKED TRANSISTOR DEVICES (17847628)

Main Inventor

Cheng-Ying Huang

Brief explanation

The patent application describes an integrated circuit structure that includes a device layer with an upper device and a lower device. The upper device has an upper source or drain region and an upper source or drain contact, while the lower device has a lower source or drain region. 

• The integrated circuit structure includes a first conductive feature below the device layer, which is connected to the lower source or drain region.
• A second conductive feature vertically extends through the device layer and connects the first conductive feature below the device layer to an interconnect structure above the device layer.
• This arrangement allows for a connection between the interconnect structure on the frontside of the integrated circuit and the lower source or drain region towards the backside of the integrated circuit.

Potential applications of this technology:

• This integrated circuit structure can be used in various electronic devices, such as smartphones, computers, and IoT devices.
• It can be applied in the manufacturing of advanced semiconductor chips for improved performance and functionality.

Problems solved by this technology:

• The integration of the first and second conductive features enables a more efficient and compact design of the integrated circuit structure.
• It provides a reliable connection between the interconnect structure and the lower source or drain region, improving overall circuit performance.

Benefits of this technology:

• The integrated circuit structure allows for better signal transmission and reduced power consumption.
• It enables higher integration density and improved functionality in electronic devices.
• The design simplifies the manufacturing process and reduces production costs.

Abstract

An integrated circuit structure includes a device layer including an upper device above a lower device. The upper device includes an upper source or drain region, and an upper source or drain contact coupled to the upper source or drain region. The lower device includes a lower source or drain region. A first conductive feature is below the device layer, where the first conductive feature is coupled to the lower source or drain region. A second conductive feature vertically extends through the device layer. In an example, the second conductive feature is to couple (i) the first conductive feature below the device layer and (ii) an interconnect structure above the device layer. Thus, the first and second conductive features facilitate a connection between the interconnect structure on the frontside of the integrated circuit and the lower source or drain region towards the backside of the integrated circuit.

SINGLE GATED 3D NANOWIRE INVERTER FOR HIGH DENSITY THICK GATE SOC APPLICATIONS (18244741)

Main Inventor

Rahul RAMASWAMY

Brief explanation

The abstract describes a semiconductor device and a method of forming such a device. The device includes a substrate and two transistors of different conductivity types. Each transistor has a semiconductor channel and a gate electrode surrounding the channel. The gate electrodes of the two transistors are made of different materials.

• The semiconductor device includes two transistors of different conductivity types.
• Each transistor has a semiconductor channel and a gate electrode surrounding the channel.
• The gate electrodes of the two transistors are made of different materials.

Potential Applications

• This technology can be used in the manufacturing of various semiconductor devices such as integrated circuits and microprocessors.
• It can be applied in the development of high-performance electronic devices that require efficient control of electrical currents.

Problems Solved

• The use of different materials for the gate electrodes of the transistors allows for improved performance and functionality of the semiconductor device.
• It addresses the need for precise control of electrical currents in semiconductor devices.

Benefits

• The use of different materials for the gate electrodes enables better optimization of the transistor's performance.
• It provides enhanced control over the electrical characteristics of the semiconductor device.
• The technology can lead to improved efficiency and reliability of electronic devices.

Abstract

Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a substrate, and a first transistor of a first conductivity type over the substrate. In an embodiment, the first transistor comprises a first semiconductor channel, and a first gate electrode around the first semiconductor channel. In an embodiment, the semiconductor device further comprises a second transistor of a second conductivity type above the first transistor. The second transistor comprises a second semiconductor channel, and a second gate electrode around the second semiconductor channel. In an embodiment, the second gate electrode and the first gate electrode comprise different materials.

GATE ALL AROUND TRANSISTORS ON ALTERNATE SUBSTRATE ORIENTATION (17847559)

Main Inventor

Ashish Agrawal

Brief explanation

The patent application describes semiconductor devices on a substrate with a different crystallographic surface orientation. This includes gate-all-around transistors such as nanoribbon and nanosheet transistors, as well as forksheet transistors. 

• The substrate used has a (110) crystallographic surface orientation.
• The growth of alternating silicon germanium (SiGe) or germanium tin (GeSn) and silicon (Si) semiconductor layers is based on this substrate.
• P-channel transistors are formed using SiGe or GeSn nanoribbons, while n-channel transistors are formed from Si nanoribbons.
• The crystallographic surface orientation of the SiGe or GeSn nanoribbons matches that of the substrate, resulting in higher hole mobility and improved device performance.

Potential Applications

• This technology can be applied in the development of advanced semiconductor devices.
• It can be used in the manufacturing of gate-all-around transistors, such as nanoribbon and nanosheet transistors.
• The technology can also be utilized in the production of forksheet transistors.

Problems Solved

• The use of a substrate with an alternative crystallographic surface orientation solves the problem of limited hole mobility in traditional semiconductor devices.
• It addresses the need for improved device performance and efficiency in semiconductor technology.

Benefits

• The technology allows for higher hole mobility across SiGe or GeSn nanoribbons, leading to improved device performance.
• It enables the growth of alternating semiconductor layers on the substrate, providing flexibility in transistor design and functionality.
• The use of different crystallographic surface orientations expands the possibilities for advanced semiconductor device development.

Abstract

Semiconductor devices on a substrate with an alternative crystallographic surface orientation. Example devices includes gate-all-around (e.g., nanoribbon and nanosheet) and forksheet transistors. In an example, a substrate having a (110) crystallographic surface orientation forms the basis for the growth of alternating silicon germanium (SiGe) or germanium tin (GeSn) and silicon (Si) semiconductor layers. P-channel transistors may be formed using SiGe or GeSn nanoribbons while n-channel transistors are formed from Si nanoribbons. The crystallographic surface orientation of the SiGe or GeSn nanoribbons will reflect the same crystallographic surface orientation of the substrate, which leads to a higher hole mobility across the SiGe or GeSn nanoribbons and improved device performance.

SELF-ASSEMBLED MONOLAYER ON A DIELECTRIC FOR TRANSITION METAL DICHALCOGENIDE GROWTH FOR STACKED 2D CHANNELS (17850078)

Main Inventor

Carl H. NAYLOR

Brief explanation

The abstract describes a patent application related to creating a transistor structure by selectively growing a 2D TMD (Transition Metal Dichalcogenide) directly in a stacked channel configuration, such as a stacked nanowire or nanoribbon formation. The growth of TMD occurs for all the nanowires or nanoribbons in the transistor structure in one stage. The use of a self-assembled monolayer (SAM) on multiple dielectric layers facilitates channel deposition and geometry in the stacked channel configuration.

• Selective growth of a 2D TMD directly in a stacked channel configuration
• Growth of TMD occurs for all nanowires or nanoribbons in the transistor structure in one stage
• Use of a self-assembled monolayer (SAM) on multiple dielectric layers facilitates channel deposition and geometry in the stacked channel configuration

Potential Applications

• Transistor manufacturing
• Semiconductor industry
• Electronics manufacturing

Problems Solved

• Simplifies the process of creating a transistor structure by growing a 2D TMD directly in a stacked channel configuration
• Enables simultaneous growth of TMD for all nanowires or nanoribbons in the transistor structure
• Facilitates channel deposition and geometry in the stacked channel configuration

Benefits

• Streamlines transistor manufacturing process
• Increases efficiency and speed of transistor production
• Enables the creation of more compact and advanced transistor structures

Abstract

Embodiments described herein may be related to apparatuses, processes, and techniques directed to creating a transistor structure by selectively growing a 2D TMD directly in a stacked channel configuration, such as a stacked nanowire or nanoribbon formation. In embodiments, this TMD growth may occur for all of the nanowires or nanoribbons in the transistor structure in one stage. Placement of a SAM on a plurality of dielectric layers within the transistor structure stack facilitates channel deposition and channel geometry in the stacked channel configuration. Other embodiments may be described and/or claimed.

STACKED SINGLE CRYSTAL TRANSITION-METAL DICHALCOGENIDE USING SEEDED GROWTH (17850623)

Main Inventor

Carl H. NAYLOR

Brief explanation

The abstract of this patent application describes a transistor structure that consists of stacked nanoribbons as a single crystal or monolayer, specifically a transition metal dichalcogenide (TMD) layer, grown on a silicon wafer using a seeding material.

• The transistor structure includes stacked nanoribbons as a single crystal or monolayer.
• The nanoribbons are made of a transition metal dichalcogenide (TMD) layer.
• The TMD layer is grown on a silicon wafer using a seeding material.

Potential Applications:

• This technology can be used in the development of high-performance transistors.
• It can be applied in the field of electronics and semiconductor devices.
• The transistor structure can be utilized in various electronic devices such as computers, smartphones, and IoT devices.

Problems Solved:

• This technology solves the problem of achieving high-performance transistors by utilizing stacked nanoribbons as a single crystal or monolayer.
• It addresses the challenge of growing a TMD layer on a silicon wafer using a seeding material.

Benefits:

• The use of stacked nanoribbons as a single crystal or monolayer improves the performance of transistors.
• The growth of a TMD layer on a silicon wafer using a seeding material provides a reliable and scalable manufacturing process.
• This technology enables the development of more efficient and powerful electronic devices.

Abstract

Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for a transistor structure that includes stacked nanoribbons as a single crystal or monolayer, such as a transition metal dichalcogenide (TMD) layer, grown on a silicon wafer using a seeding material. Other embodiments may be described and/or claimed.

INTEGRATED CIRCUIT STRUCTURE WITH BACKSIDE POWER STAPLE (17850778)

Main Inventor

Sukru YEMENICIOGLU

Brief explanation

The patent application describes integrated circuit structures with a backside power staple. Here are the key points:

• The integrated circuit structure includes gate lines and trench contacts.
• The trench contacts are placed over the source or drain structures, alternating with the gate lines.
• A front-side metal routing layer extends over the gate lines and is connected to the trench contacts.
• A backside metal routing layer runs beneath the gate lines and trench contacts, parallel and overlapping with the front-side metal routing layer.
• A conductive feedthrough structure connects the backside metal routing layer to the front-side metal routing layer.

Potential applications of this technology:

• Integrated circuits in various electronic devices such as smartphones, computers, and IoT devices.
• Power management systems in electronic devices.
• High-performance computing systems.

Problems solved by this technology:

• Efficient power distribution within integrated circuits.
• Improved performance and reliability of integrated circuits.
• Enhanced power management capabilities.

Benefits of this technology:

• More efficient power delivery, reducing power losses and improving overall performance.
• Enhanced reliability and stability of integrated circuits.
• Improved power management capabilities, allowing for better control and optimization of power usage.

Abstract

Integrated circuit structures having backside power staple are described. In an example, an integrated circuit structure includes a plurality of gate lines. A plurality of trench contacts is extending over a plurality of source or drain structures, individual ones of the plurality of trench contacts alternating with individual ones of the plurality of gate lines. A front-side metal routing layer is extending over one or more of the plurality of gate lines, and over and coupled to one or more of the plurality of trench contacts. A backside metal routing layer is extending beneath the one or more of the plurality of gate lines and the one or more of the plurality of trench contacts, the backside metal routing layer parallel and overlapping with the front-side metal routing layer. A conductive feedthrough structure couples the backside metal routing layer to the front-side metal routing layer.

2D LAYERED GATE OXIDE (17852016)

Main Inventor

Chelsey DOROW

Brief explanation

The abstract of this patent application describes a transistor device that includes a transition metal dichalcogenide (TMD) channel, a two-dimensional (2D) dielectric layer over the TMD channel, and a gate metal layer over the 2D dielectric.

• The transistor device includes a TMD channel.
• The TMD channel is a type of material used in the construction of the transistor.
• The transistor device also includes a 2D dielectric layer.
• The 2D dielectric layer is positioned over the TMD channel.
• The transistor device further includes a gate metal layer.
• The gate metal layer is positioned over the 2D dielectric layer.

Potential Applications

• This transistor device can be used in various electronic devices, such as smartphones, tablets, and computers.
• It can be utilized in integrated circuits and microprocessors.
• The technology can be applied in the field of telecommunications and wireless communication devices.

Problems Solved

• The transistor device addresses the need for improved performance and efficiency in electronic devices.
• It solves the problem of achieving higher speeds and lower power consumption in integrated circuits.
• The technology helps overcome limitations of traditional transistor designs.

Benefits

• The use of a TMD channel and 2D dielectric layer can enhance the performance of the transistor device.
• It can lead to faster switching speeds and reduced power consumption.
• The technology offers potential for smaller and more efficient electronic devices.

Abstract

Embodiments disclosed herein include transistor devices. In an embodiment, the transistor comprises a transition metal dichalcogenide (TMD) channel. In an embodiment, a two dimensional (2D) dielectric is over the TMD channel. In an embodiment, a gate metal is over the 2D dielectric.

SELF-ALIGNED EMBEDDED SOURCE AND DRAIN CONTACTS (17851658)

Main Inventor

Nitesh Kumar

Brief explanation

Abstract:

An integrated circuit structure has a contact for a source or drain region, where the contact has an upper portion outside the source or drain region and a lower portion extending within the source or drain region. The lower portion of the contact is surrounded by the source or drain region, creating a close adjacency between the contact and the source or drain region.

• The integrated circuit structure includes a contact for a source or drain region.
• The contact has an upper portion outside the source or drain region.
• The contact also has a lower portion that extends within the source or drain region.
• The lower portion of the contact is surrounded by the source or drain region.
• The close adjacency between the contact and the source or drain region is achieved by the source or drain region wrapping around the lower portion of the contact.

Potential Applications:

• This integrated circuit structure can be used in various electronic devices such as smartphones, computers, and IoT devices.
• It can be applied in the manufacturing of microprocessors, memory chips, and other integrated circuits.
• The technology can be utilized in the development of advanced semiconductor devices for high-performance computing, artificial intelligence, and telecommunications.

Problems Solved:

• The integrated circuit structure solves the problem of inefficient contact between the source or drain region and the contact.
• It addresses the issue of limited surface area for contact in small-scale integrated circuits.
• The technology provides a solution for improving the electrical performance and reliability of integrated circuits.

Benefits:

• The close adjacency between the contact and the source or drain region enhances the electrical connectivity and efficiency of the integrated circuit.
• The improved contact design allows for better control of current flow and reduces resistance, leading to enhanced performance.
• The technology enables higher integration density and miniaturization of integrated circuits, leading to more compact and efficient electronic devices.

Abstract

An integrated circuit structure includes a source or drain region, and a contact for the source or drain region. The contact has (i) an upper portion outside the source or drain region and (ii) a lower portion extending within the source or drain region. For example, the source or drain region wraps around the lower portion of the contact, such that an entire perimeter of the lower portion of the contact is adjacent to the source or drain region.

FABRICATION OF GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING COMMON METAL GATES AND HAVING GATE DIELECTRICS WITH AN OPPOSITE POLARITY DIPOLE LAYER (17850769)

Main Inventor

Dan S. LAVRIC

Brief explanation

The abstract describes gate-all-around integrated circuit structures with common metal gates and gate dielectrics containing a dipole layer. The structure includes two vertical arrangements of horizontal nanowires, each with a gate stack. The first gate stack is for PMOS and includes a P-type conductive layer on a gate dielectric with an N-type dipole material layer. The second gate stack is for NMOS and also includes the P-type conductive layer on a gate dielectric with the N-type dipole material layer and an additional N-type dipole material layer.

• Gate-all-around integrated circuit structures with common metal gates and gate dielectrics containing a dipole layer
• Two vertical arrangements of horizontal nanowires with separate gate stacks for PMOS and NMOS
• PMOS gate stack includes P-type conductive layer and gate dielectric with N-type dipole material layer
• NMOS gate stack includes P-type conductive layer and gate dielectric with N-type dipole material layer and an additional N-type dipole material layer

Potential Applications

• Integrated circuits
• Semiconductor devices

Problems Solved

• Improved performance and efficiency of integrated circuits
• Enhanced control over the flow of current in PMOS and NMOS devices

Benefits

• Common metal gates simplify manufacturing processes
• Gate dielectrics with dipole layers improve device performance
• Allows for better control and optimization of PMOS and NMOS devices

Abstract

Gate-all-around integrated circuit structures having common metal gates and having gate dielectrics with a dipole layer are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, the first gate stack a PMOS gate stack having a P-type conductive layer on a first gate dielectric including a first N-type dipole material layer. A second gate stack is over the second vertical arrangement of horizontal nanowires, the second gate stack an NMOS gate stack having the P-type conductive layer on a second gate dielectric including the first N-type dipole material layer and a second N-type dipole material layer.

INTEGRATED CIRCUIT STRUCTURES HAVING AOI GATES WITH ROUTING ACROSS NANOWIRES (17851960)

Main Inventor

Abhishek Anil SHARMA

Brief explanation

The patent application describes a structure for integrated circuits that includes nanowires and gate stacks with cuts in a vertical direction. 

• The structure includes a stack of horizontal nanowires arranged vertically.
• A gate stack is placed over the horizontal nanowires, surrounding the channel region of each wire.
• The gate stack has one or more cuts in the vertical direction.

Potential Applications

This technology has potential applications in various fields, including:

• Integrated circuit manufacturing
• Nanoelectronics
• Semiconductor industry

Problems Solved

The technology addresses the following problems:

• Efficient routing of signals across nanowires in integrated circuits
• Enhancing the performance and functionality of integrated circuits
• Overcoming limitations in traditional gate stack designs

Benefits

The technology offers several benefits, including:

• Improved signal routing capabilities across nanowires
• Enhanced performance and functionality of integrated circuits
• Increased efficiency in integrated circuit manufacturing processes

Abstract

Structures having AOI gates with routing across nanowires are described. In an example, an integrated circuit structure includes a stack of horizontal nanowires along a vertical direction. A gate stack is over the stack of horizontal nanowires and is surrounding a channel region of each of the horizontal nanowires, the gate stack having one or more cuts in the vertical direction.

GATE CUT AND FIN TRIM ISOLATION FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION (18367292)

Main Inventor

Tahir GHANI

Brief explanation

==Abstract Explanation==

This patent application is related to the fabrication of advanced integrated circuit structures, specifically those with a size of 10 nanometers or smaller. The method described involves forming multiple fins and gate structures over these fins. A dielectric material structure is then formed between the gate structures. Portions of the gate structures are removed to expose different portions of the fins. The exposed first portion of each fin is removed, while the exposed second portion is not removed.

Bullet Points

• The patent application is about a method for fabricating advanced integrated circuit structures.
• It specifically focuses on structures with a size of 10 nanometers or smaller.
• The method involves forming multiple fins and gate structures over these fins.
• A dielectric material structure is formed between the gate structures.
• Portions of the gate structures are removed to expose different portions of the fins.
• The exposed first portion of each fin is removed, while the exposed second portion is not removed.

Potential Applications

• This technology can be applied in the fabrication of advanced integrated circuits with a size of 10 nanometers or smaller.
• It can be used in the production of high-performance electronic devices, such as smartphones, tablets, and computers.
• The method described in the patent application can enable the creation of more compact and efficient integrated circuit structures.

Problems Solved

• The method addresses the challenge of fabricating integrated circuit structures with a size of 10 nanometers or smaller.
• It solves the problem of exposing different portions of the fins while maintaining the desired structure.
• The method provides a solution for removing specific portions of the gate structures to achieve the desired circuit configuration.

Benefits

• The technology allows for the fabrication of advanced integrated circuits with improved performance and efficiency.
• It enables the creation of smaller and more compact electronic devices.
• The method described in the patent application offers a precise and controlled approach to fabricating integrated circuit structures.

Abstract

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, a method includes forming a plurality of fins and forming a plurality of gate structures over the plurality of fins. A dielectric material structure is formed between adjacent ones of the plurality of gate structures. A portion of a first of the plurality of gate structures is removed to expose a first portion of each of the plurality of fins, and a portion of a second of the plurality of gate structures is removed to expose a second portion of each of the plurality of fins. The exposed first portion of each of the plurality of fins is removed, but the exposed second portion of each of the plurality of fins is not removed.

DIFFUSION CUT STRESSORS FOR STACKED TRANSISTORS (17809329)

Main Inventor

Cheng-Ying Huang

Brief explanation

The patent application describes techniques for creating non-planar semiconductor devices in a stacked transistor configuration next to stressor materials. The configuration includes an n-channel device and a p-channel device, both of which are gate-all-around transistors with nanoribbons extending in the same direction. The n-channel device is positioned vertically above the p-channel device (or vice versa), and source or drain regions are located adjacent to both ends of each device.

• The patent application proposes a stacked transistor configuration with gate-all-around transistors.
• The configuration includes nanoribbons extending in the same direction.
• The n-channel and p-channel devices are positioned vertically above each other.
• Source or drain regions are located adjacent to both ends of each device.
• Stressor materials are used on the opposite side of the stacked source or drain regions to fill the gate trench.
• The stressor materials may include a compressive stressor material adjacent to the p-channel device and/or a tensile stressor material adjacent to the n-channel device.
• The stressor material(s) may form part of a diffusion cut structure.

Potential Applications

• Semiconductor manufacturing
• Integrated circuit design
• Transistor fabrication

Problems Solved

• Non-planar semiconductor devices can be challenging to fabricate.
• Stacked transistor configurations can introduce stress-related issues.
• Diffusion cut structures may be difficult to implement effectively.

Benefits

• Improved performance and efficiency of semiconductor devices.
• Enhanced control over stress effects in stacked transistor configurations.
• Simplified fabrication process for non-planar semiconductor devices.

Abstract

Techniques are provided herein to form non-planar semiconductor devices in a stacked transistor configuration adjacent to stressor materials. In one example, an n-channel device and a p-channel device may both be gate-all-around transistors each having any number of nanoribbons extending in the same direction, where the n-channel device is located vertically above the p-channel device (or vice versa). Source or drain regions are adjacent to both ends of the n-channel device and both ends of the p-channel device. On the opposite side of the stacked source or drain regions (e.g., opposite from the nanoribbons), stressor materials may be used to fill the gate trench in place of additional semiconductor devices. The stressor materials may include, for instance, a compressive stressor material adjacent to the p-channel device and/or a tensile stressor material adjacent to the n-channel device. The stressor material(s) may form or otherwise be part of a diffusion cut structure.

MOBILITY IMPROVEMENT IN GATE ALL AROUND TRANSISTORS BASED ON SUBSTRATE ORIENTATION (17847555)

Main Inventor

Seung Hoon Sung

Brief explanation

The patent application describes techniques for forming semiconductor devices on a substrate with a specific crystallographic surface orientation, particularly for gate-all-around and forksheet transistor configurations. The substrate has a (110) crystallographic surface orientation, which allows for the growth of alternating types of semiconductor layers.

• The techniques are useful for fabricating both n-channel and p-channel transistors using silicon nanoribbons formed from the alternating semiconductor layers.
• The crystallographic surface orientation of the Si nanoribbons matches that of the substrate, resulting in higher hole mobility across the Si nanoribbons of the p-channel devices and improved CMOS device performance.

Potential Applications

• Semiconductor device manufacturing
• Transistor fabrication
• CMOS device production

Problems Solved

• Limited hole mobility in p-channel transistors
• Lower overall CMOS device performance

Benefits

• Improved hole mobility in p-channel devices
• Enhanced CMOS device performance

Abstract

Techniques are provided herein to form semiconductor devices on a substrate with an alternative crystallographic surface orientation. The techniques are particularly useful with respect to gate-all-around and forksheet transistor configurations. A substrate having a (110) crystallographic surface orientation forms the basis for the growth of alternating types of semiconductor layers. Both n-channel and p-channel transistors may be fabricated using silicon nanoribbons formed from some of the alternating semiconductor layers. The crystallographic surface orientation of the Si nanoribbons will reflect the same crystallographic surface orientation of the substrate, which leads to a higher hole mobility across the Si nanoribbons of the p-channel devices and an overall improved CMOS device performance.

VARACTOR DEVICE WITH BACKSIDE ELECTRICAL CONTACT (17848660)

Main Inventor

Ayan Kar

Brief explanation

The abstract describes a varactor device that includes various components such as a support structure, semiconductor structures, contact structures, and a semiconductor region. These components work together to create a varactor device with specific functionalities.

• The varactor device includes a support structure and an electrically conductive layer at the backside of the support structure.
• Two semiconductor structures, made of doped semiconductor materials, are present in the device.
• Two contact structures, which are electrically conductive, are connected to the semiconductor structures.
• One of the contact structures connects the corresponding semiconductor structure to the electrically conductive layer.
• A semiconductor region is located between the two semiconductor structures and can be connected to both of them.
• The semiconductor region may consist of non-planar semiconductor structures coupled with a gate.
• The gate is connected to another electrically conductive layer at the frontside of the support structure.
• The varactor device may also include a pair of additional semiconductor regions that are electrically insulated from each other.
• These additional semiconductor regions can be coupled to two oppositely polarized gates, respectively.

Potential Applications

• The varactor device can be used in various electronic circuits and systems that require voltage-controlled capacitance.
• It can be utilized in frequency synthesizers, voltage-controlled oscillators, and tunable filters.
• The device can also find applications in wireless communication systems, radar systems, and other RF/microwave applications.

Problems Solved

• The varactor device solves the problem of providing voltage-controlled capacitance in electronic circuits.
• It addresses the need for tunable components that can adjust their capacitance based on the applied voltage.
• The device offers a compact and efficient solution for voltage-controlled capacitance requirements.

Benefits

• The varactor device provides a high level of control over capacitance, allowing for precise tuning and adjustment.
• It offers a compact and integrated design, reducing the need for additional components.
• The device can operate at high frequencies, making it suitable for RF/microwave applications.
• It provides improved performance and reliability compared to traditional varactor devices.

Abstract

A varactor device includes a support structure, an electrically conductive layer at the backside of the support structure, two semiconductor structures including doped semiconductor materials, two contact structures, and a semiconductor region. Each contract structure is electrically conductive and is connected to a different one of the semiconductor structures A contract structure couples the corresponding semiconductor structure to the electrically conductive layer. The semiconductor region is between the two semiconductor structures and can be connected to the two semiconductor structures. The semiconductor region may include non-planar semiconductor structures coupled with a gate. The gate may be coupled to another electrically conductive layer at the frontside of the support structure. The varactor device may further include a pair of additional semiconductor regions that are electrically insulated from each other. The additional semiconductor regions may be coupled to two oppositely polarized gates, respectively.

DEVICE, SYSTEM AND METHOD TO DELIVER POWER WITH PHASE CIRCUITS OF AN INTEGRATED CIRCUIT DIE (17851997)

Main Inventor

Tamir Salus

Brief explanation

The abstract describes techniques and mechanisms for delivering current to an inductor of a voltage regulator in a scalable manner. 

• The integrated circuit (IC) die has a hardware interface that allows it to be connected to multiple inductors.
• The hardware interface consists of contacts that connect the IC die to the respective inductors.
• The IC die includes a phase circuit with multiple cells, each connected to a different contact of the hardware interface.
• A digital controller in the IC die can select different combinations of cells to conduct current with the corresponding contacts.
• In another embodiment, the contacts are arranged in a multi-row, multi-column array.

Potential applications of this technology:

• Power management systems
• Voltage regulators
• Power supply units
• Electronic devices requiring efficient current delivery

Problems solved by this technology:

• Scalable delivery of current to multiple inductors
• Efficient utilization of the IC die's resources
• Flexibility in selecting different combinations of cells for current conduction

Benefits of this technology:

• Scalability in delivering current to multiple inductors
• Improved efficiency in power management
• Flexibility in configuring the IC die for different applications

Abstract

Techniques and mechanisms for facilitating a scalable delivery of current to an inductor of a voltage regulator. In an embodiment, a hardware interface of integrated circuit (IC) die accommodates coupling of the IC die to multiple inductors. The hardware interface comprises contacts which are each to couple the IC die to a respective one of the multiple inductors. A phase circuit of the IC die includes multiple cells which are each coupled to a different respective contact of a plurality of contacts of the hardware interface. A digital controller of the IC die is operable to select any of various combinations of the multiple cells each to conduct a respective current with a corresponding one of the plurality of contacts. In another embodiment, the plurality of contacts are arranged as a multi-row, multi-column array.

AUTO PHASE SCALING FOR DYNAMIC VOLTAGE ID (17982318)

Main Inventor

Patrick Kam-shing Leung

Brief explanation

The abstract of the patent application describes various embodiments of apparatuses, systems, and methods for automatic phase scaling (APS) of dynamic voltage ID (DVID) in a voltage regulator. These embodiments aim to improve the efficiency and performance of voltage regulators by automatically adjusting the phase scaling of the voltage regulator based on dynamic voltage ID.

• Automatic phase scaling (APS) technology for dynamic voltage ID (DVID) in a voltage regulator.
• Apparatuses, systems, and methods for implementing APS in voltage regulators.
• APS adjusts the phase scaling of the voltage regulator based on dynamic voltage ID.
• Improves the efficiency and performance of voltage regulators.
• Provides automatic adjustment of phase scaling, eliminating the need for manual intervention.
• Can be implemented in various types of voltage regulators.
• Enhances the stability and reliability of voltage regulation systems.

Potential Applications

• Power management systems
• Electronic devices and appliances
• Renewable energy systems
• Electric vehicles
• Industrial automation and control systems

Problems Solved

• Manual adjustment of phase scaling in voltage regulators can be time-consuming and prone to errors.
• Inefficient phase scaling can lead to poor voltage regulation and reduced system performance.
• Lack of automatic adjustment of phase scaling can limit the adaptability of voltage regulators to changing load conditions.

Benefits

• Improved efficiency and performance of voltage regulators.
• Automatic adjustment of phase scaling based on dynamic voltage ID.
• Enhanced stability and reliability of voltage regulation systems.
• Simplified operation and reduced manual intervention.
• Increased adaptability to changing load conditions.

Abstract

Various embodiments provide apparatuses, systems, and methods for automatic phase scaling (APS) of dynamic voltage ID (DVID) in a voltage regulator. Other embodiments may be described and claimed.

SYSTEMS, APPARATUS, ARTICLES OF MANUFACTURE, AND METHODS FOR PRIVATE NETWORK MOBILITY MANAGEMENT (18343586)

Main Inventor

Stephen Palermo

Brief explanation

The patent application describes methods and systems for managing mobility in a private network. It introduces a "private network in a box" that includes circuitry to communicate with terrestrial and non-terrestrial network nodes, as well as programmable circuitry and machine-readable instructions.

• The programmable circuitry generates two separate meshes associated with different geographical areas of the private network.
• It aligns multi-access terrestrial network (TN) nodes with the first mesh and non-terrestrial network (NTN) nodes with the second mesh.
• The programmable circuitry enables communication for user equipment within either of the meshes using the private network.

Potential Applications

• Private network mobility management for organizations or communities.
• Enabling seamless communication within a private network across different geographical areas.
• Supporting communication for user equipment within the private network.

Problems Solved

• Efficient management of mobility within a private network.
• Facilitating communication between different types of network nodes (TN and NTN).
• Enabling seamless communication for user equipment within the private network.

Benefits

• Simplified and efficient management of mobility in a private network.
• Improved communication capabilities within the private network.
• Flexibility in aligning network nodes based on geographical areas.
• Enhanced user experience and connectivity within the private network.

Abstract

Methods, apparatus, systems, and articles of manufacture are disclosed for private network mobility management. An example private network in a box includes interface circuitry to communicate with multi-access terrestrial network (TN) nodes and non-terrestrial network (NTN) nodes, machine readable instructions, and programmable circuitry. The example programmable circuitry is to generate a first mesh associated with a geographical area of the private network and a second mesh associated with the geographical area. The example programmable circuitry is also to initiate at least one of the multi-access TN nodes in alignment with the first mesh and at least one of the NTN nodes in alignment with the second mesh. Additionally, the example programmable circuitry is to facilitate communication associated with at least one user equipment within at least one of the first mesh or the second mesh using the private network.

TECHNOLOGIES FOR ALLOCATING RESOURCES ACROSS DATA CENTERS (18238096)

Main Inventor

Anjaneya Reddy CHAGAM REDDY

Brief explanation

The patent application describes technologies for efficiently allocating resources across data centers. Here are the key points:

• The technology involves a compute device that collects data on resource utilization for a managed node executing a workload.
• The compute device analyzes the available resources in the data center where it is located and determines if they meet the resource utilization data.
• If the available resources are insufficient, the compute device allocates additional resources from an off-premises data center.
• The off-premises data center is different from the data center where the compute device is located.

Potential applications of this technology:

• Cloud computing: The technology can be used to dynamically allocate resources to different nodes in a cloud environment based on their workload requirements.
• Data center management: It can help optimize resource allocation across multiple data centers, ensuring efficient utilization and minimizing downtime.

Problems solved by this technology:

• Resource optimization: The technology addresses the challenge of efficiently allocating resources to meet the demands of different workloads.
• Scalability: By leveraging resources from an off-premises data center, the technology enables scaling up resources without relying solely on the local data center's capacity.

Benefits of this technology:

• Improved efficiency: By dynamically allocating resources, the technology ensures that workloads have the necessary resources to operate optimally.
• Enhanced scalability: The ability to allocate resources from an off-premises data center allows for seamless scaling of resources as needed.
• Cost savings: The technology enables efficient resource utilization, reducing the need for overprovisioning and potentially lowering operational costs.

Abstract

Technologies for allocating resources across data centers include a compute device to obtain resource utilization data indicative of a utilization of resources for a managed node to execute a workload. The compute device is also to determine whether a set of resources presently available to the managed node in a data center in which the compute device is located satisfies the resource utilization data. Additionally, the compute device is to allocate, in response to a determination that the set of resources presently available to the managed node does not satisfy the resource utilization data, a supplemental set of resources to the managed node. The supplemental set of resources are located in an off-premises data center that is different from the data center in which the compute device is located. Other embodiments are also described and claimed.

CONCEPT FOR A TELEMETRY HUB FOR MICROSERVICES (17809297)

Main Inventor

Rajesh POORNACHANDRAN

Brief explanation

The abstract describes a patent application related to a computer system and a telemetry hub apparatus. The telemetry hub is designed to collect telemetry information from multiple microservices and provide access to this information based on an access scheme.

• The patent application is related to a computer system and a telemetry hub apparatus.
• The telemetry hub collects telemetry information from various microservices.
• The telemetry hub provides access to the collected telemetry information for the microservices.
• The access to the telemetry information is based on an access scheme.

Potential Applications

• Monitoring and analyzing the performance of multiple microservices in a computer system.
• Identifying and resolving issues or bottlenecks in the microservices.
• Optimizing the overall performance and efficiency of the computer system.

Problems Solved

• Efficiently collecting telemetry information from multiple microservices.
• Providing a centralized hub for accessing and managing the telemetry information.
• Enabling effective monitoring and analysis of the microservices' performance.

Benefits

• Simplifies the process of collecting and accessing telemetry information from multiple microservices.
• Enhances the ability to monitor and analyze the performance of microservices.
• Facilitates the identification and resolution of issues or bottlenecks in the microservices.
• Improves the overall performance and efficiency of the computer system.

Abstract

Examples relate to a computer system, a telemetry hub apparatus, a telemetry hub device, a telemetry hub method, a microservice apparatus, a microservice device, a microservice method and to corresponding computer programs. The telemetry apparatus is configured to obtain telemetry information from a plurality of microservices, and to provide access to the telemetry information for the plurality of microservices according to an access scheme.

TECHNOLOGIES FOR PROTOCOL EXECUTION WITH AGGREGATION AND CACHING (18356587)

Main Inventor

Matthias Schunter

Brief explanation

The patent application describes technologies for executing protocols using a command device and multiple computing devices. Here are the key points:

• The command device broadcasts a protocol message to multiple computing devices.
• The command device receives an aggregated status message from an aggregation system.
• The aggregated status message indicates the success or failure of executing the instructions corresponding to the protocol message.
• Failed computing devices are uniquely identified in the aggregated status message.
• The success of the remaining computing devices is aggregated into a single success identifier.

Potential applications of this technology:

• Distributed computing systems
• Internet of Things (IoT) networks
• Cloud computing environments

Problems solved by this technology:

• Efficiently executing protocols across multiple computing devices
• Identifying and addressing failures in protocol execution

Benefits of this technology:

• Improved reliability and efficiency in protocol execution
• Simplified monitoring and management of protocol execution across multiple devices
• Enhanced troubleshooting capabilities for identifying and resolving failures in protocol execution.

Abstract

Technologies for protocol execution include a command device to broadcast a protocol message to a plurality of computing devices and receive an aggregated status message from an aggregation system. The aggregated status message identifies a success or failure of execution of instructions corresponding with the protocol message by the plurality of computing devices such that each computing device of the plurality of computing devices that failed is uniquely identified and the success of remaining computing devices is aggregated into a single success identifier.

PACKET PROCESSING WITH REDUCED LATENCY (18243896)

Main Inventor

Eliezer Tamir

Brief explanation

==Abstract==

This patent application describes a technology for packet processing with reduced latency. It introduces a device that includes a data queue, an interrupt generation circuit, and an interrupt delay register.

• The device has a data queue to store data descriptors associated with data packets.
• The data packets are transferred between a network and a driver circuit.
• An interrupt generation circuit is included to generate an interrupt to the driver circuit.
• The interrupt is generated when a delay timer expires and the data queue is not empty.
• An interrupt delay register enables the driver circuit to reset the delay timer, postponing the interrupt generation.

Potential Applications

• Network devices and routers that require efficient packet processing.
• Real-time applications that demand low latency, such as video streaming or online gaming.
• Cloud computing infrastructure to optimize data transfer between servers.

Problems Solved

• Reduces latency in packet processing, improving overall network performance.
• Ensures timely processing of data packets, minimizing delays and improving user experience.
• Optimizes the utilization of network resources by efficiently managing data queues.

Benefits

• Reduced latency in packet processing, leading to faster data transfer and improved network performance.
• Enhanced user experience in real-time applications with reduced delays.
• Efficient utilization of network resources, improving overall network efficiency.

Abstract

Generally, this disclosure provides devices, methods, and computer readable media for packet processing with reduced latency. The device may include a data queue to store data descriptors associated with data packets, the data packets to be transferred between a network and a driver circuit. The device may also include an interrupt generation circuit to generate an interrupt to the driver circuit. The interrupt may be generated in response to a combination of an expiration of a delay timer and a non-empty condition of the data queue. The device may further include an interrupt delay register to enable the driver circuit to reset the delay timer, the reset postponing the interrupt generation.

SECURE STREAM PROTOCOL FOR SERIAL INTERCONNECT (18345278)

Main Inventor

Vedvyas Shanbhogue

Brief explanation

The abstract describes a patent application for a secure stream protocol for a serial interconnect. The protocol aims to secure transactions between devices by using an end-to-end protocol and separating the transactions into different secure streams. The first device in the transaction process secures the transaction based on its type and sends it to the second device over a link. The transaction may pass through intermediate devices before reaching the second device.

• The patent application describes a secure stream protocol for a serial interconnect.
• The protocol uses an end-to-end approach to secure transactions between devices.
• Transactions are separated into different secure streams.
• The first device in the transaction process secures the transaction based on its type.
• The secured transaction is sent to the second device over a link.
• The transaction may traverse one or more intermediate devices before reaching the second device.
• The first secure stream can be based on different transaction types, such as posted, non-posted, or completion transaction types.

Potential Applications

• Secure communication between devices in a serial interconnect system.
• Protection of sensitive data during transactions.
• Secure transfer of financial transactions or personal information.

Problems Solved

• Ensuring the security of transactions in a serial interconnect system.
• Preventing unauthorized access or tampering of transaction data.
• Addressing the potential vulnerabilities of intermediate devices in the transaction process.

Benefits

• Enhanced security for transactions between devices.
• Separation of transactions into different secure streams for improved organization and protection.
• End-to-end protocol ensures the security of transactions throughout the process.

Abstract

Methods, systems, and apparatuses associated with a secure stream protocol for a serial interconnect are disclosed. An apparatus comprises a first device comprising circuitry to, using an end-to-end protocol, secure a transaction in a first secure stream based at least in part on a transaction type of the transaction, where the first secure stream is separate from a second secure stream. The first device is further to send the transaction secured in the first secure stream to a second device over a link established between the first device and the second device, where the transaction is to traverse one or more intermediate devices from the first device to the second device. In more specific embodiments, the first secure stream is based on one of a posted transaction type, a non-posted transaction type, or completion transaction type.

TECHNOLOGIES FOR ACCELERATED HTTP PROCESSING WITH HARDWARE ACCELERATION (18202408)

Main Inventor

Parthasarathy Sarangam

Brief explanation

The patent application describes technologies for accelerating the processing of HTTP messages using a computing device and a network controller. Here is a simplified explanation of the abstract:

• The computing device generates an HTTP message and converts it into a transport protocol packet like TCP/IP or QUIC.
• The network controller compresses the HTTP header of the message and encrypts it before transmitting it to a remote device.
• The network controller can segment the transport protocol packet into multiple segmented packets for transmission.
• It can also receive encrypted transport protocol packets and decrypt them to obtain the compressed HTTP message.
• The network controller then decompresses the HTTP message and directs it to a receive queue based on the contents of the HTTP header.
• It can also coalesce multiple transport protocol packets for efficient processing.

Potential applications of this technology:

• Accelerating the processing of HTTP messages in various network environments.
• Improving the performance and efficiency of web applications and services.
• Enhancing the speed and responsiveness of web browsing and content delivery.

Problems solved by this technology:

• Slow processing of HTTP messages can lead to delays in web applications and services.
• Large HTTP headers can consume significant network bandwidth and increase latency.
• Encryption and compression of HTTP messages can improve security and reduce data transmission overhead.

Benefits of this technology:

• Faster processing of HTTP messages, leading to improved performance and user experience.
• Reduced network bandwidth consumption through compression and encryption.
• Enhanced security and privacy of HTTP messages during transmission.
• Efficient handling of large HTTP headers and segmented packets for optimized network utilization.

Abstract

Technologies for accelerated HTTP message processing include a computing device having a network controller. The computing device may generate an HTTP message, frame the HTTP message to generate a transport protocol packet such as a TCP/IP packet or QUIC packet, and pass the transport protocol packet to the network controller. The network controller compresses the HTTP header of the HTTP message, encrypts the compressed HTTP message, and transmits the encrypted message to a remote device. The network controller may segment the transport protocol packet into multiple segmented packets. The network controller may receive transport protocol packets that include encrypted HTTP message. The network controller decrypts the encrypted HTTP message to generate a compressed HTTP message, decompresses the HTTP message, and steers the HTTP message to a receive queue based on contents of an HTTP header. The network controller may coalesce multiple transport protocol packets. Other embodiments are described and claimed.

METHODS AND ARRANGEMENTS FOR SHORT BEACON FRAMES IN WIRELESS NETWORKS (18242998)

Main Inventor

MINYOUNG PARK

Brief explanation

==Abstract==

The patent application describes a new format for short beacon frames in wireless communication devices. These frames are used to transmit information between devices. The application also explains how the frames are created, stored, received, and transmitted.

Explanation

• The patent application introduces a new format for short beacon frames in wireless communication devices.
• The frames are built by a medium access control (MAC) sublayer logic in the first communication device.
• The frame control field of the frames contains information about the type of frame (extension frame) and the subtype (short beacon).
• The frame control field may also include a service set identifier (SSID) control field and a reserved field.
• The short beacon frames can be stored in memory or logic to facilitate their transmission.
• The communication devices can receive and detect communications with the short beacon frames.
• The devices can also generate and transmit communications using the short beacon frames.

Potential Applications

• Wireless communication devices can use the new short beacon frame format to improve their communication efficiency.
• The format can be implemented in various devices such as smartphones, laptops, routers, and IoT devices.
• It can be used in different wireless communication protocols such as Wi-Fi, Bluetooth, and Zigbee.
• The technology can be applied in various industries including telecommunications, home automation, healthcare, and transportation.

Problems Solved

• The new short beacon frame format provides a more efficient way of transmitting information between wireless communication devices.
• It simplifies the frame structure and reduces the overhead associated with transmitting beacon frames.
• The format allows for faster and more reliable communication between devices.
• It improves the overall performance and throughput of wireless networks.

Benefits

• The new format improves the efficiency and reliability of wireless communication devices.
• It reduces the complexity and overhead of transmitting beacon frames.
• The technology enables faster and more responsive communication between devices.
• It enhances the overall performance and throughput of wireless networks.

Abstract

Embodiments provide a new short beacon frame format and its operation with full beacon frame transmissions for wireless communications devices. Many embodiments comprise a medium access control (MAC) sublayer logic to build frames comprising the short beacon frame for a first communications device. In some embodiments, the MAC sublayer may determine a frame control field comprising a type field indicative of an extension frame and a subtype indicative of a short beacon. In further embodiments, the frame control field may comprise a service set identifier (SSID) control field, and a reserved field. Some embodiments may store the short beacon frame or frame format in memory, in logic, or in another manner that facilitates transmission of the short beacon frames. Some embodiments may receive and detect communications with the short beacon frames. Further embodiments may generate and transmit a communication with the short beacon frames.

ADAPTIVE RESOLUTION OF POINT CLOUD AND VIEWPOINT PREDICTION FOR VIDEO STREAMING IN COMPUTING ENVIRONMENTS (18347278)

Main Inventor

MAYURESH VARERKAR

Brief explanation

The patent application describes a mechanism for enhancing the viewing experience of immersive media in computing environments. It involves analyzing the user's viewing positions and determining the relevance of different parts of the media content based on these positions. The relevant portions are then predicted and transmitted for rendering and display.

• The mechanism analyzes the user's viewing positions with respect to a display.
• It determines the relevance of different parts of the media content based on the viewing positions.
• The media content includes immersive videos captured by cameras.
• The mechanism predicts and transmits the relevant portions of the media content for rendering and display.

Potential Applications

• Virtual reality (VR) and augmented reality (AR) applications.
• Gaming and interactive entertainment.
• Training and simulation environments.
• Remote collaboration and communication platforms.

Problems Solved

• Enhances the viewing experience of immersive media by adapting the resolution and viewpoint based on the user's viewing positions.
• Improves the efficiency of rendering and displaying media content by transmitting only the relevant portions.

Benefits

• Provides a more immersive and personalized viewing experience for users.
• Reduces bandwidth and processing requirements by transmitting and rendering only the relevant portions of the media content.
• Enables more efficient utilization of computing resources in immersive media applications.

Abstract

A mechanism is described for facilitating adaptive resolution and viewpoint-prediction for immersive media in computing environments. An apparatus of embodiments, as described herein, includes one or more processors to receive viewing positions associated with a user with respect to a display, and analyze relevance of media contents based on the viewing positions, where the media content includes immersive videos of scenes captured by one or more cameras. The one or more processors are further to predict portions of the media contents as relevant portions based on the viewing positions and transmit the relevant portions to be rendered and displayed.

ADAPTIVE FOVEATED ENCODER AND GLOBAL MOTION PREDICTOR (18345880)

Main Inventor

Yunbiao Lin

Brief explanation

The abstract of this patent application describes an adaptive video encoder that can determine headset-related information, such as focus and motion, and adjust video encode parameters accordingly. 

• The technology can determine headset-related information, such as focus and motion.
• Based on this information, the video encoder can determine one or more video encode parameters.
• The patent application also mentions other embodiments of the technology.

Potential Applications

This technology has potential applications in various fields, including:

• Virtual reality (VR) and augmented reality (AR) headsets: The adaptive video encoder can optimize video encoding parameters based on the user's focus and motion, providing a better immersive experience.
• Video streaming platforms: By adjusting video encode parameters based on headset-related information, the video quality can be optimized for different devices and viewing conditions.
• Video conferencing systems: The adaptive video encoder can adapt to the user's headset-related information, ensuring a smoother and more efficient video conferencing experience.

Problems Solved

The technology addresses several problems, including:

• Inefficient video encoding: Traditional video encoders may not consider headset-related information, resulting in suboptimal video quality and performance.
• Inconsistent video experience: Different headsets and user behaviors can affect the video experience, and the adaptive video encoder solves this problem by adjusting encode parameters accordingly.
• Limited bandwidth utilization: By adapting video encoding parameters based on headset-related information, the technology can optimize bandwidth utilization and improve video streaming efficiency.

Benefits

The benefits of this technology include:

• Improved video quality: By considering headset-related information, the adaptive video encoder can optimize video encoding parameters, resulting in higher quality video.
• Enhanced user experience: The technology ensures a more immersive and consistent video experience by adapting to the user's focus and motion.
• Efficient bandwidth usage: By dynamically adjusting video encode parameters, the technology optimizes bandwidth utilization, leading to smoother video streaming and reduced data consumption.

Abstract

An embodiment of an adaptive video encoder may include technology to determine headset-related information including at least one of focus-related information and motion-related information, and determine one or more video encode parameters based on the headset-related information. Other embodiments are disclosed and claimed.

CYBER ATTACK DETECTION FUNCTION (18465766)

Main Inventor

Abhijeet Kolekar

Brief explanation

The abstract describes a technique for detecting cyber attacks in a cellular network. Here are the key points:

• The technique involves a cyber attack detection function (CDAF) in the cellular network.
• The CDAF identifies operation state data from an analytics logical function (AnLF), which is an output of an analytics process.
• Based on the operation state data, the CDAF identifies a cyber attack on at least one element of the cellular network.
• Once a cyber attack is identified, the CDAF transmits a report that includes an indication of the cyber attack.
• The patent application mentions that there may be other embodiments or variations of this technique.

Potential applications of this technology:

• Enhancing the security of cellular networks by detecting and reporting cyber attacks.
• Protecting sensitive user data and preventing unauthorized access to network resources.
• Improving the overall reliability and performance of cellular networks by identifying and mitigating cyber threats.

Problems solved by this technology:

• Cyber attacks on cellular networks can lead to data breaches, service disruptions, and other security issues. This technique helps in early detection and response to such attacks.
• Traditional security measures may not be sufficient to detect sophisticated cyber attacks. The CDAF provides an additional layer of security by analyzing operation state data from the AnLF.

Benefits of this technology:

• Early detection of cyber attacks allows for prompt response and mitigation, minimizing the potential damage.
• By identifying cyber attacks on specific elements of the cellular network, targeted security measures can be implemented to protect those elements.
• The CDAF can provide valuable insights into the nature and patterns of cyber attacks, enabling network operators to improve their security strategies.

Abstract

Various embodiments herein provide techniques related to a cellular network. Specifically, a cyber attack detection function (CDAF) of the cellular network may be configured to: identify operation state data from an analytics logical function (AnLF), wherein the operation state data corresponds to an analytics output of the AnLF; identify, based on the operation state data, a cyber-attack of at least one element of the cellular network; and transmit, based on the identification of the cyber-attack, a report that includes an indication of the cyber-attack. Other embodiments may be described and/or claimed.

TECHNIQUES FOR INTEGRATED ACCESS AND BACKHAUL (IAB) NODES (18450318)

Main Inventor

Wei Mao

Brief explanation

==Abstract==

Various embodiments provide techniques for integrated access and backhaul (IAB) nodes. These techniques include:

• Rate-proportional routing for network coding
• Utilizing multiple routes in IAB networks
• User equipment (UE) and parent selection for efficient topology in IAB networks
• Establishing efficient IAB topologies
• Adaptive coded-forwarding for network coding

Potential Applications

This technology has potential applications in the field of integrated access and backhaul (IAB) networks. It can be used in various scenarios where efficient routing, network coding, and topology optimization are required. Some potential applications include:

• Wireless communication networks
• Internet of Things (IoT) networks
• Mobile networks
• Rural broadband connectivity

Problems Solved

The techniques described in this patent application address several problems in integrated access and backhaul (IAB) networks, including:

• Inefficient routing and network coding
• Limited capacity and throughput
• Suboptimal topology and connectivity
• Lack of adaptability and flexibility in network design

Benefits

The benefits of this technology include:

• Improved network performance and efficiency
• Increased capacity and throughput
• Enhanced connectivity and coverage
• Adaptive and flexible network design

Abstract

Various embodiments herein provide techniques for integrated access and backhaul (IAB) nodes. For example, embodiments include techniques associated with: rate-proportional routing for network coding; utilizing multiple routes in IAB networks; user equipment (UE) and parent selection for efficient topology in IAB networks; establishing efficient IAB topologies; and/or adaptive coded-forwarding for network coding. Other embodiments may be described and claimed.

LOW POWER WAKE-UP SIGNAL WITH TWO PARTS IN TIME DOMAIN (18465698)

Main Inventor

Yingyang Li

Brief explanation

==Abstract==

Various embodiments provide techniques for a low power wake-up signal (LP-WUS) with two parts. The LP-WUS is received by a wake-up receiver of a user equipment (UE) and used to trigger a main receiver of the UE to wake up or enter a higher power state. The first part indicates the presence and/or other characteristics of the second part. The first and second parts are transmitted in one or more symbols, slots, or time resource units.

Explanation

• The patent application describes a method for using a low power wake-up signal (LP-WUS) to wake up a main receiver in a user equipment (UE).
• The LP-WUS consists of two parts, with the first part indicating the presence and characteristics of the second part.
• The LP-WUS is received by a wake-up receiver in the UE, which then triggers the main receiver to wake up or enter a higher power state.
• The first and second parts of the LP-WUS are transmitted in one or more symbols, slots, or time resource units.

Potential Applications

• This technology can be applied in various wireless communication systems, such as cellular networks, IoT devices, and wireless sensor networks.
• It can be used to efficiently wake up specific devices or receivers in a network, reducing overall power consumption.
• LP-WUS can enable energy-efficient communication in battery-powered devices, extending their battery life.

Problems Solved

• Traditional wake-up signals often require high power consumption, which is not suitable for battery-powered devices.
• Existing wake-up techniques may lack the ability to indicate the presence and characteristics of the main signal, leading to inefficient power usage.
• This technology solves these problems by providing a low power wake-up signal with two parts, allowing for efficient triggering of main receivers.

Benefits

• The LP-WUS enables energy-efficient communication by minimizing power consumption during idle periods.
• It allows for targeted wake-up of specific devices or receivers, reducing unnecessary power usage.
• By indicating the presence and characteristics of the main signal, the LP-WUS optimizes power usage and improves overall system efficiency.

Abstract

Various embodiments herein provide techniques for a low power wake-up signal (LP-WUS) with two parts. The LP-WUS may be received by a wake-up receiver of a user equipment (UE) and used to trigger a main receiver of the UE to wake up (e.g., turn on or enter a higher power state). The first part may be used to indicate the presence and/or other characteristics of the second part. The first and second parts may each be transmitted in one or more symbols, slots, or time resource units. Other embodiments may be described and claimed.

COLD PLATES FOR SECONDARY SIDE COMPONENTS OF PRINTED CIRCUIT BOARDS (18344308)

Main Inventor

Prabhakar Subrahmanyam

Brief explanation

The abstract describes a patent application for cold plates used in printed circuit boards. These cold plates are specifically designed for the secondary side components of the circuit boards.

• The patent application focuses on cold plates for secondary side components of printed circuit boards.
• An example apparatus includes a first printed circuit board and a second printed circuit board coupled to it.
• The second printed circuit board has a first side and a second side, with the second side facing the first printed circuit board.
• A cold plate is coupled to the second side of the second printed circuit board.

Potential Applications

• This technology can be applied in various electronic devices that utilize printed circuit boards.
• It can be used in computers, servers, telecommunications equipment, and other electronic systems.

Problems Solved

• The cold plates help in dissipating heat generated by the secondary side components of printed circuit boards.
• They address the issue of thermal management, preventing overheating and potential damage to the components.

Benefits

• The use of cold plates improves the overall thermal performance of the printed circuit boards.
• It helps in maintaining the temperature within safe limits, enhancing the reliability and lifespan of the components.
• The technology allows for more efficient cooling, which can lead to improved performance and reduced energy consumption.

Abstract

Cold plates for secondary side components of printed circuit boards are disclosed herein. An example apparatus disclosed herein includes a first printed circuit board, a second printed circuit board coupled to the first printed circuit board, the second printed circuit board having a first side and a second side opposite the first side, the second side facing the first printed circuit board, and a cold plate coupled to the second side of the second printed circuit board.

INTEGRATED CIRCUIT STRUCTURES HAVING INVERTERS WITH CONTACTS BETWEEN NANOWIRES (17851979)

Main Inventor

Abhishek Anil SHARMA

Brief explanation

The patent application describes a structure for integrated circuits that includes nanowires and inverters with contacts between them. Here is a simplified explanation of the abstract:

• The integrated circuit structure consists of a stack of horizontal nanowires arranged vertically.
• A conductive contact is placed next to a source or drain region of the nanowire stack, with a cut in the vertical direction.
• A gate stack surrounds the channel region of each horizontal nanowire, and it is spaced apart from the conductive contact.

Potential applications of this technology:

• Integrated circuits: The described structure can be used in the development of advanced integrated circuits.
• Nanoelectronics: This technology can contribute to the advancement of nanoelectronic devices.

Problems solved by this technology:

• Improved performance: The structure with nanowires and inverters can enhance the performance of integrated circuits.
• Miniaturization: The use of nanowires allows for smaller and more compact circuit designs.

Benefits of this technology:

• Higher efficiency: The structure enables improved efficiency in integrated circuits.
• Enhanced functionality: The use of nanowires and inverters provides additional functionality to integrated circuits.
• Compact design: The technology allows for smaller and more space-efficient circuit designs.

Abstract

Structures having inverters with contacts between nanowires are described. In an example, an integrated circuit structure includes a stack of horizontal nanowires along a vertical direction. A conductive contact is laterally adjacent to a source or drain region of the stack of horizontal nanowires, the conductive contact having a cut in the vertical direction. A gate stack is over the stack of horizontal nanowires and surrounding a channel region of each of the horizontal nanowires, the gate stack laterally spaced apart from the conductive contact.

STATIC RANDOM-ACCESS MEMORY DEVICES WITH ANGLED TRANSISTORS (18312847)

Main Inventor

Abhishek A. Sharma

Brief explanation

The patent application describes SRAM devices with angled transistors, which can increase the density of SRAM cells on semiconductor chips. 

• The transistors in the SRAM cells are referred to as "angled" because their elongated semiconductor structure is built at an angle other than 0 degrees or 90 degrees with respect to the edges of the support structure or die.
• The angle can range between about 10 and 80 degrees with respect to at least one of the edges.
• Implementing angled transistors in SRAM cells can help increase the density of these cells on semiconductor chips, which have limited space.

Potential Applications

• Semiconductor chip manufacturing
• Memory devices
• Integrated circuits

Problems Solved

• Limited real estate on semiconductor chips for SRAM cells
• Increasing the density of SRAM cells without compromising performance

Benefits

• Increased density of SRAM cells on semiconductor chips
• Improved performance of SRAM devices
• Cost-effective manufacturing process

Abstract

SRAM devices with angled transistors, and related assemblies and methods, are disclosed herein. A transistor is referred to as “angled” if a longitudinal axis of an elongated semiconductor structure (e.g., a fin or a nanoribbon) based on which the transistor is built is at an angle other than 0 degrees or 90 degrees with respect to the edges of front or back faces of a support structure or a die on/in which the transistor resides, e.g., at an angle between about 10 and 80 degrees with respect to at least one of such edges. Implementing at least some of the transistors of SRAM cells as angled transistors may provide a promising way to increasing densities of SRAM cells on the limited real estate of semiconductor chips.

INTEGRATED CIRCUIT STRUCTURES HAVING MEMORY WITH BACKSIDE DRAM AND POWER DELIVERY (17851967)

Main Inventor

Abhishek Anil SHARMA

Brief explanation

The patent application describes a structure that combines memory and power delivery in an integrated circuit. The structure includes a front-side structure with nanowire-based transistors and metallization layers, and a backside structure with dynamic random access memory (DRAM) devices.

• The integrated circuit structure includes nanowire-based transistors and DRAM devices.
• The front-side structure contains the nanowire-based transistors and metallization layers.
• The backside structure is located below the nanowire-based transistors and includes the DRAM devices.
• The nanowire-based transistors provide the processing power, while the DRAM devices provide memory storage.
• The combination of memory and power delivery in a single structure improves the efficiency and performance of the integrated circuit.

Potential Applications

• This technology can be used in various electronic devices, such as smartphones, tablets, and computers.
• It can be applied in data centers and servers to enhance their processing and memory capabilities.
• The structure can be utilized in artificial intelligence systems, autonomous vehicles, and other advanced technologies that require high-performance computing and memory.

Problems Solved

• The integration of memory and power delivery in a single structure reduces the need for separate components, saving space and improving efficiency.
• The combination of nanowire-based transistors and DRAM devices enhances the performance and functionality of the integrated circuit.
• The structure addresses the increasing demand for higher processing power and memory capacity in electronic devices.

Benefits

• Improved efficiency and performance due to the integration of memory and power delivery.
• Space-saving design by eliminating the need for separate memory and power components.
• Enhanced processing power and memory capacity for advanced technologies and applications.

Abstract

Structures having memory with backside DRAM and power delivery are described. In an example, an integrated circuit structure includes a front-side structure including a device layer having a plurality of nanowire-based transistors, and a plurality of metallization layers above the nanowire-based transistors of the device layer. A backside structure is below the nanowire-based transistors of the device layer. The backside structure includes a plurality of dynamic random access memory (DRAM) devices.

LOGIC CIRCUITS USING VERTICAL TRANSISTORS WITH BACKSIDE SOURCE OR DRAIN REGIONS (18314862)

Main Inventor

Sagar Suthram

Brief explanation

==Abstract==

IC devices with logic circuits using vertical transistors with backside source or drain (S/D) regions are disclosed. The vertical transistor includes an elongated structure of semiconductor material extending between a first side and an opposing second side of a substrate. The first S/D region is provided at the first side of the substrate, while the second S/D region is provided at the second side, with the channel region of the transistor being the portion of the elongated structure between the first and second S/D regions. This technology aims to increase transistor densities on semiconductor chips and decrease short-channel effects associated with continuous scaling of IC components.

Bullet Points

• IC devices with logic circuits using vertical transistors with backside S/D regions are disclosed.
• The vertical transistor includes an elongated structure of semiconductor material extending between a first side and an opposing second side of a substrate.
• The first S/D region is provided at the first side of the substrate, while the second S/D region is provided at the second side.
• The channel region of the transistor is the portion of the elongated structure between the first and second S/D regions.
• This technology aims to increase transistor densities on semiconductor chips.
• This technology aims to decrease short-channel effects associated with continuous scaling of IC components.

Potential Applications

• Integrated circuit (IC) devices
• Logic circuits
• Semiconductor chips

Problems Solved

• Limited real estate on semiconductor chips for increasing transistor densities
• Short-channel effects associated with continuous scaling of IC components

Benefits

• Increased transistor densities on semiconductor chips
• Decreased short-channel effects

Abstract

IC devices with logic circuits using vertical transistors with backside source or drain (S/D) regions, and related assemblies and methods, are disclosed herein. An example vertical transistor includes an elongated structure (e.g., a nanoribbon) of one or more semiconductor materials extending between a first side (e.g., a back side) and an opposing second side (e.g., a front side) of a substrate. The first S/D region of the transistor may be provided at the first side of the substrate, while the second S/D region of the transistor may be provided at the second side, with the channel region of the transistor being the portion of the elongated structure between the first and second S/D regions. Implementing various logic circuits using vertical transistors with backside S/D regions may provide a promising way to increasing densities of transistors on the limited real estate of semiconductor chips and/or decreasing short-channel effects associated with continuous scaling of IC components.

LARGE GRAIN AND HALOGEN-FREE SILICON CELL CHANNEL FOR 3D NAND STRING (18367319)

Main Inventor

Jessica S. Kachian

Brief explanation

The abstract of the patent application describes an apparatus that includes an array of linear cell channels and a string of NAND memory cells arranged along a cell channel. The apparatus utilizes a polysilicon cell channel layer with specific characteristics, such as a low halogen atom count, a thin thickness, and a high grain height mean.

• The apparatus includes an array of linear cell channels and a string of NAND memory cells.
• The cell channels are made of a polysilicon layer with less than E17 halogen atoms per cubic centimeter.
• The thickness of the polysilicon layer is equal to or less than 25 nanometers.
• The polysilicon layer has an area-weighted grain height mean greater than 30 nanometers.

Potential Applications:

• This technology can be applied in the field of memory devices, specifically NAND memory cells.
• It can be used in various electronic devices, such as smartphones, tablets, and computers, to enhance memory storage capabilities.

Problems Solved:

• The use of a low halogen atom count in the polysilicon layer reduces potential harmful effects and improves the overall safety of the apparatus.
• The thin thickness of the polysilicon layer allows for more compact and efficient memory cell designs.
• The high grain height mean of the polysilicon layer enhances the performance and reliability of the memory cells.

Benefits:

• The low halogen atom count improves the safety and environmental impact of the apparatus.
• The thin polysilicon layer enables smaller and more efficient memory cell designs, leading to space-saving benefits in electronic devices.
• The high grain height mean enhances the performance and reliability of the memory cells, resulting in improved data storage and retrieval capabilities.

Abstract

An example of an apparatus may include an array of linear cell channels and a string of NAND memory cells arranged along a cell channel of the array of linear cell channels, where a polysilicon cell channel layer comprises material with less than E17 halogen atoms per cubic centimeter, where a thickness of the polysilicon cell channel layer is less than or equal to 25 nanometers, and where an area-weighted grain height mean of the polysilicon cell channel layer is greater than 30 nanometers. Other examples are disclosed and claimed.

SEMICONDUCTOR STRUCTURE INCLUDING BARRIER LAYER BETWEEN ELECTRODE LAYER AND UNDERLYING SUBSTRATE (17850746)

Main Inventor

Shafaat Ahmed

Brief explanation

The abstract describes a semiconductor structure that includes a substrate with circuitry and a semiconductor stack on top of it. The stack consists of a first electrically conductive layer made of metal, which is connected to the circuitry of the substrate. There is also a second electrically conductive layer between the substrate and the first layer, made of either a refractory metal or a combination of silicon, carbon, and nitride. This second layer acts as a barrier to prevent intermixing between the metal of the first layer and the substrate material during the deposition process.

• The semiconductor structure includes a substrate with circuitry and a semiconductor stack.
• The stack consists of a first electrically conductive layer made of metal.
• There is a second electrically conductive layer between the substrate and the first layer.
• The second layer is made of either a refractory metal or a combination of silicon, carbon, and nitride.
• The second layer acts as a barrier to prevent intermixing between the metal of the first layer and the substrate material during deposition.

Potential Applications

• Semiconductor manufacturing
• Integrated circuit fabrication
• Electronics industry

Problems Solved

• Formation of intermixing regions between metal layers and substrate material during deposition
• Improved reliability and performance of semiconductor structures

Benefits

• Enhanced barrier properties to prevent intermixing
• Improved overall performance and reliability of semiconductor devices
• Simplified manufacturing process

Abstract

A semiconductor structure, system and method. The semiconductor structure comprises: a substrate including circuitry therein; and a semiconductor stack on the substrate, the semiconductor stack including: a first electrically conductive layer including a metal and electrically coupled to the circuitry of the substrate; and a second electrically conductive layer between the substrate and the first electrically conductive layer, the second electrically conductive layer including one of a refractory metal, or a combination including silicon, carbon and nitride. The second electrically conductive layer may serve as a barrier layer between the first electrically conductive layer and the material of the underlying substrate, in this manner avoiding the formation of an intermixing region between the metal of the first electrically conductive layer and the material of the substrate during deposition of the metal.