17846303. SINGLE LITHOGRAPHY METHODS FOR INTERCONNECT ARCHITECTURES simplified abstract (Intel Corporation)
Contents
SINGLE LITHOGRAPHY METHODS FOR INTERCONNECT ARCHITECTURES
Organization Name
Inventor(s)
Suddhasattwa Nad of Chandler AZ (US)
Jason Steill of Phoenix AZ (US)
SINGLE LITHOGRAPHY METHODS FOR INTERCONNECT ARCHITECTURES - A simplified explanation of the abstract
This abstract first appeared for US patent application 17846303 titled 'SINGLE LITHOGRAPHY METHODS FOR INTERCONNECT ARCHITECTURES
Simplified Explanation
The patent application describes a semiconductor assembly interconnect structure that includes a substrate, a metallic layer, an adhesion promoter film, a solder resist layer, and a stacked electrical connector. The method of making this interconnect structure involves patterning the metallic layer, depositing an adhesion promoter layer, patterning the adhesion promoter layer, and depositing a surface finish layer.
- The interconnect structure includes a substrate, metallic layer, adhesion promoter film, solder resist layer, and stacked electrical connector.
- The metallic layer is patterned on the substrate.
- An adhesion promoter layer is deposited on the metallic layer.
- The adhesion promoter layer is patterned to expose selected portions of the metallic layer.
- A surface finish layer is deposited on the exposed selected portions of the metallic layer.
Potential applications of this technology:
- Semiconductor manufacturing
- Electronics assembly
- Circuit board production
Problems solved by this technology:
- Improved adhesion between the metallic layer and other layers
- Enhanced electrical connectivity
- Increased reliability of the interconnect structure
Benefits of this technology:
- Stronger bond between layers
- Improved performance and durability of semiconductor assemblies
- More efficient and reliable electrical connections
Original Abstract Submitted
Various embodiments disclosed relate to a semiconductor assembly interconnect structure. The present disclosure includes an interconnect structure that case include a substrate, a metallic layer thereon, an adhesion promoter film formed over the metallic layer and forming a flat region over a flat portion of the metallic layer, a solder resist layer formed over the adhesion promoter film, an opening in the solder resist layer and the adhesion promoter film in the flat region of the adhesion promotion film, the opening connecting to the flat portion of the metallic layer, and a stacked electrical connector formed on the metallic layer within the opening. Methods of making an interconnect structure can include patterning a metallic layer on a substrate, depositing an adhesion promoter layer on the metallic layer opposite the substrate, patterning the adhesion promoter layer to expose selected portions of the metallic layer, and depositing a surface finish layer on the exposed selected portions of the metallic layer.
