17846173. PACKAGE ARCHITECTURE OF PHOTONIC SYSTEM WITH VERTICALLY STACKED DIES HAVING PLANARIZED EDGES simplified abstract (Intel Corporation)

PACKAGE ARCHITECTURE OF PHOTONIC SYSTEM WITH VERTICALLY STACKED DIES HAVING PLANARIZED EDGES

Organization Name

Intel Corporation

Inventor(s)

Sagar Suthram of Portland OR (US)

Ravindranath Vithal Mahajan of Chandler AZ (US)

Debendra Mallik of Chandler AZ (US)

Omkar G. Karhade of Chandler AZ (US)

Wilfred Gomes of Portland OR (US)

Pushkar Sharad Ranade of San Jose CA (US)

Abhishek A. Sharma of Hillsboro OR (US)

Tahir Ghani of Portland OR (US)

Anand S. Murthy of Portland OR (US)

Nitin A. Deshpande of Chandler AZ (US)

PACKAGE ARCHITECTURE OF PHOTONIC SYSTEM WITH VERTICALLY STACKED DIES HAVING PLANARIZED EDGES - A simplified explanation of the abstract

This abstract first appeared for US patent application 17846173 titled 'PACKAGE ARCHITECTURE OF PHOTONIC SYSTEM WITH VERTICALLY STACKED DIES HAVING PLANARIZED EDGES

Simplified Explanation

The abstract describes embodiments of an integrated circuit (IC) die that consist of multiple regions and interfaces.

• The first region of the IC die has two surfaces, with the first surface being perpendicular to the second surface.
• The second region is made of semiconductor material and is attached to the first region along a planar interface that is parallel to the second surface and perpendicular to the first surface.
• The third region contains optical structures of a photonic IC and is attached to the second region along a planar interface that is parallel to the first planar interface.
• The first region includes multiple layers of conductive traces in a dielectric material, with each layer being parallel to the second surface and perpendicular to the first surface.
• The first surface of the first region has bond-pads, which are portions of the conductive traces exposed on the surface.

Potential applications of this technology:

• Integrated circuits with improved optical capabilities.
• Photonic integrated circuits with enhanced functionality.
• High-speed data communication and processing applications.
• Optoelectronic devices and systems.

Problems solved by this technology:

• Integration of optical structures into an IC die.
• Efficient coupling of optical and electronic components.
• Enhanced performance and functionality of integrated circuits.

Benefits of this technology:

• Improved data transfer rates and processing speeds.
• Compact and integrated design.
• Higher efficiency and reliability.
• Enables the development of advanced optoelectronic systems.

Original Abstract Submitted

Embodiments of an integrated circuit (IC) die comprise a first region having a first surface and a second surface, the first surface being orthogonal to the second surface; a second region comprising a semiconductor material, the second region attached to the first region along a first planar interface that is orthogonal to the first surface and parallel to the second surface; and a third region comprising optical structures of a photonic IC, the third region attached to the second region along a second planar interface that is parallel to the first planar interface. The first region comprises: a plurality of layers of conductive traces in a dielectric material, each layer of the conductive traces being parallel to the second surface such that the conductive traces are orthogonal to the first surface; and bond-pads on the first surface, the bond-pads comprising portions of respective conductive traces exposed on the first surface.