17847282. PACKAGING ARCHITECTURE WITH ROUNDED TRACES FOR ON-PACKAGE HIGH-SPEED INTERCONNECTS simplified abstract (Intel Corporation)
PACKAGING ARCHITECTURE WITH ROUNDED TRACES FOR ON-PACKAGE HIGH-SPEED INTERCONNECTS
Organization Name
Inventor(s)
Cemil Geyik of Gilbert AZ (US)
Zhiguo Qian of Chandler AZ (US)
Kristof Kuwawi Darmawikarta of Chandler AZ (US)
Zhichao Zhang of Chandler AZ (US)
PACKAGING ARCHITECTURE WITH ROUNDED TRACES FOR ON-PACKAGE HIGH-SPEED INTERCONNECTS - A simplified explanation of the abstract
This abstract first appeared for US patent application 17847282 titled 'PACKAGING ARCHITECTURE WITH ROUNDED TRACES FOR ON-PACKAGE HIGH-SPEED INTERCONNECTS
Simplified Explanation
The patent application describes a microelectronic assembly that includes a package substrate, a conductive trace, a conductive structure, and an integrated circuit (IC) die.
- The package substrate has a first face and a second face, and it contains a conductive trace embedded in a dielectric material.
- The conductive structure surrounds the conductive trace and is separated from it by the dielectric material.
- The IC die is attached to the first face of the package substrate and connected to the conductive trace through a conductive pathway within the substrate.
- The conductive trace has a non-rectangular cross-section with rounded corners, while the conductive structure consists of multiple conductive planes parallel to the trace and connected to a ground connection.
Potential applications of this technology:
- Microelectronic devices and systems
- Integrated circuits and electronic components
- Semiconductor packaging and assembly
Problems solved by this technology:
- Improved electrical performance and signal integrity
- Enhanced thermal management and heat dissipation
- Reduction of electromagnetic interference (EMI) and noise
Benefits of this technology:
- Higher reliability and durability of microelectronic assemblies
- Increased functionality and miniaturization of electronic devices
- Improved manufacturing efficiency and cost-effectiveness
Original Abstract Submitted
Embodiments of a microelectronic assembly comprise: a package substrate having a first face and an opposing second face, the package substrate comprising a conductive trace in a dielectric material, a conductive structure at least partially surrounding the conductive trace and separated from the conductive trace by the dielectric material; and an integrated circuit (IC) die attached to the first face of the package substrate and coupled to the conductive trace by a conductive pathway through the package substrate. The conductive trace has a non-rectangular cross-section with rounded corners, the conductive structure comprises a plurality of conductive planes parallel to the conductive trace and coupled to a ground connection.
