17847555. MOBILITY IMPROVEMENT IN GATE ALL AROUND TRANSISTORS BASED ON SUBSTRATE ORIENTATION simplified abstract (Intel Corporation)

MOBILITY IMPROVEMENT IN GATE ALL AROUND TRANSISTORS BASED ON SUBSTRATE ORIENTATION

Organization Name

Intel Corporation

Inventor(s)

Seung Hoon Sung of Portland OR (US)

Ashish Agrawal of Hillsboro OR (US)

Jack T. Kavalieros of Portland OR (US)

Rambert Nahm of Beaverton OR (US)

Natalie Briggs of Hillsboro OR (US)

Susmita Ghose of Hillsboro OR (US)

Glenn Glass of Portland OR (US)

Devin R. Merrill of McMinnville OR (US)

Aaron A. Budrevich of Portland OR (US)

Shruti Subramanian of Hillsboro OR (US)

Biswajeet Guha of Hillsboro OR (US)

William Hsu of Portland OR (US)

Adedapo A. Oni of North Plains OR (US)

Rahul Ramamurthy of Hillsboro OR (US)

Anupama Bowonder of Portland OR (US)

Hsin-Ying Tseng of Hillsboro OR (US)

Rajat K. Paul of Portland OR (US)

Marko Radosavljevic of Portland OR (US)

MOBILITY IMPROVEMENT IN GATE ALL AROUND TRANSISTORS BASED ON SUBSTRATE ORIENTATION - A simplified explanation of the abstract

This abstract first appeared for US patent application 17847555 titled 'MOBILITY IMPROVEMENT IN GATE ALL AROUND TRANSISTORS BASED ON SUBSTRATE ORIENTATION

Simplified Explanation

The patent application describes techniques for forming semiconductor devices on a substrate with a specific crystallographic surface orientation, particularly for gate-all-around and forksheet transistor configurations. The substrate has a (110) crystallographic surface orientation, which allows for the growth of alternating types of semiconductor layers.

• The techniques are useful for fabricating both n-channel and p-channel transistors using silicon nanoribbons formed from the alternating semiconductor layers.
• The crystallographic surface orientation of the Si nanoribbons matches that of the substrate, resulting in higher hole mobility across the Si nanoribbons of the p-channel devices and improved CMOS device performance.

Potential Applications

• Semiconductor device manufacturing
• Transistor fabrication
• CMOS device production

Problems Solved

• Limited hole mobility in p-channel transistors
• Lower overall CMOS device performance

Benefits

• Improved hole mobility in p-channel devices
• Enhanced CMOS device performance

Original Abstract Submitted

Techniques are provided herein to form semiconductor devices on a substrate with an alternative crystallographic surface orientation. The techniques are particularly useful with respect to gate-all-around and forksheet transistor configurations. A substrate having a (110) crystallographic surface orientation forms the basis for the growth of alternating types of semiconductor layers. Both n-channel and p-channel transistors may be fabricated using silicon nanoribbons formed from some of the alternating semiconductor layers. The crystallographic surface orientation of the Si nanoribbons will reflect the same crystallographic surface orientation of the substrate, which leads to a higher hole mobility across the Si nanoribbons of the p-channel devices and an overall improved CMOS device performance.