18339454. DATA LOCALITY ENHANCEMENT FOR GRAPHICS PROCESSING UNITS simplified abstract (Intel Corporation)

DATA LOCALITY ENHANCEMENT FOR GRAPHICS PROCESSING UNITS

Organization Name

Intel Corporation

Inventor(s)

Christopher J. Hughes of Santa Clara CA (US)

Prasoonkumar Surti of Folsom CA (US)

Guei-Yuan Lueh of San Jose CA (US)

Adam T. Lake of Portland OR (US)

Jill Boyce of Portland OR (US)

Subramaniam Maiyuran of Gold River CA (US)

Lidong Xu of BEIJING (CN)

James M. Holland of Folsom CA (US)

Vasanth Ranganathan of El Dorado Hills CA (US)

Nikos Kaburlasos of Folsom CA (US)

Altug Koker of El Dorado Hills CA (US)

Abhishek R. Appu of El Dorado Hills CA (US)

DATA LOCALITY ENHANCEMENT FOR GRAPHICS PROCESSING UNITS - A simplified explanation of the abstract

This abstract first appeared for US patent application 18339454 titled 'DATA LOCALITY ENHANCEMENT FOR GRAPHICS PROCESSING UNITS

Simplified Explanation

The abstract describes an apparatus that includes multiple processing resources, a memory, and a processor. The processor receives data dependencies for tasks executing on different processing resources and moves data output from one processing resource to a cache memory connected to another processing resource.

• The apparatus includes multiple processing resources, a memory, and a processor.
• The processor receives data dependencies for tasks executing on different processing resources.
• The apparatus moves data output from one processing resource to a cache memory connected to another processing resource.

Potential applications of this technology:

• High-performance computing systems
• Distributed computing environments
• Data-intensive applications
• Parallel processing systems

Problems solved by this technology:

• Efficient data transfer between processing resources
• Minimizing data dependencies and bottlenecks
• Improving overall system performance

Benefits of this technology:

• Faster execution of tasks by reducing data transfer time
• Improved utilization of processing resources
• Enhanced scalability and performance in distributed systems
• Optimal utilization of cache memory for improved efficiency

Original Abstract Submitted

Embodiments described herein provide an apparatus comprising a plurality of processing resources including a first processing resource and a second processing resource, a memory communicatively coupled to the first processing resource and the second processing resource, and a processor to receive data dependencies for one or more tasks comprising one or more producer tasks executing on the first processing resource and one or more consumer tasks executing on the second processing resource and move a data output from one or more producer tasks executing on the first processing resource to a cache memory communicatively coupled to the second processing resource. Other embodiments may be described and claimed.