17848069. MICROELECTRONIC ASSEMBLIES WITH ANCHOR LAYER AROUND A BRIDGE DIE simplified abstract (Intel Corporation)

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MICROELECTRONIC ASSEMBLIES WITH ANCHOR LAYER AROUND A BRIDGE DIE

Organization Name

Intel Corporation

Inventor(s)

Benjamin T. Duong of Phoenix AZ (US)

Kristof Kuwawi Darmawikarta of Chandler AZ (US)

Srinivas V. Pietambaram of Chandler AZ (US)

MICROELECTRONIC ASSEMBLIES WITH ANCHOR LAYER AROUND A BRIDGE DIE - A simplified explanation of the abstract

This abstract first appeared for US patent application 17848069 titled 'MICROELECTRONIC ASSEMBLIES WITH ANCHOR LAYER AROUND A BRIDGE DIE

Simplified Explanation

The patent application describes microelectronic assemblies and methods for their fabrication. Here are the key points:

  • The microelectronic assembly includes a substrate with a cavity, a first die nested in the cavity, and a liner layer on the substrate and around the first die.
  • The liner layer is made of silicon or aluminum, and may contain nitrogen, oxygen, and carbon.
  • A second layer is formed on the liner layer and extends into the cavity, and a second die is placed on the second layer.
  • The conductive contacts on the first die are electrically coupled to the second die through conductive vias in the second layer and the liner layer.

Potential applications of this technology:

  • Microelectronics manufacturing
  • Semiconductor packaging
  • Integrated circuit fabrication

Problems solved by this technology:

  • Provides a protective liner layer for the first die and the cavity, preventing damage and improving reliability.
  • Enables electrical coupling between the first and second dies through conductive vias, facilitating communication and data transfer.

Benefits of this technology:

  • Enhanced reliability and durability of microelectronic assemblies
  • Improved electrical connectivity between different components
  • Enables miniaturization and integration of multiple dies in a single assembly.


Original Abstract Submitted

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first layer of a substrate having a cavity; a first die at least partially nested in the cavity in the first layer of the substrate, the first die having a surface with conductive contacts; a liner layer on the first layer, in a portion of the cavity, and on and around the first die, wherein a material of the liner layer includes: silicon or aluminum, and one or more of nitrogen, oxygen, and carbon; a second layer on the liner layer, wherein the second layer extends into the cavity and is on and around the first die; and a second die on the second layer, wherein the second die is electrically coupled to the conductive contacts on the first die by conductive vias through the second layer and the liner layer.

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