17851739. MULTICORE SYNCHRONIZATION MECHANISM FOR TIME CRITICAL RADIO SYSTEMS simplified abstract (Intel Corporation)
Contents
MULTICORE SYNCHRONIZATION MECHANISM FOR TIME CRITICAL RADIO SYSTEMS
Organization Name
Inventor(s)
Kevin Kinney of Coopersburg PA (US)
Zoran Zivkovic of Hertogenbosch (NL)
MULTICORE SYNCHRONIZATION MECHANISM FOR TIME CRITICAL RADIO SYSTEMS - A simplified explanation of the abstract
This abstract first appeared for US patent application 17851739 titled 'MULTICORE SYNCHRONIZATION MECHANISM FOR TIME CRITICAL RADIO SYSTEMS
Simplified Explanation
The patent application describes a hybrid architecture that combines a programmable processing array and a hardware accelerator. This architecture uses a data-driven synchronization process to maintain synchronization between the programmable elements (PEs) of the processing array. It also implements timers to ensure that the synchronization between the PEs meets the time-based requirements of the overall system.
- The hybrid architecture combines a programmable processing array and a hardware accelerator.
- A data-driven synchronization process is used to maintain synchronization between the programmable elements.
- Timers are implemented to ensure that the synchronization meets the time-based requirements of the system.
- The timers introduce a delay or latency to the processing time of each PE, forcing the hardware blocks to wait for the processed data samples.
- The hardware blocks then perform their computations based on the received data.
Potential applications of this technology:
- High-performance computing systems
- Signal processing applications
- Artificial intelligence and machine learning systems
- Data analytics and big data processing
Problems solved by this technology:
- Maintaining synchronization between programmable elements in a hybrid architecture
- Meeting time-based synchronization requirements in a data-driven system
Benefits of this technology:
- Improved performance and efficiency in processing tasks
- Enhanced synchronization between programmable elements
- Ability to meet time-based requirements in data-driven systems
Original Abstract Submitted
Techniques are disclosed for the use of a hybrid architecture that combines a programmable processing array and a hardware accelerator. The hybrid architecture implements a data driven synchronization process to maintain synchronization between the programmable elements (PEs) of the programmable processing array. The hybrid architecture implements a timer-based solution to ensure data-driven synchronization between the PEs of the programmable processing array meets the time-based synchronization requirements of the overall system. The timers function to introduce a delay or latency to the time required by each of the PEs of the programmable processing array to perform their respective tasks, thereby forcing the hardware blocks to wait to receive the processed data samples output via the PEs and perform their hardware-based computations.
