17852039. SINX ADHESION PROMOTER WITH ADHESION HOLE FEATURES IN PACKAGING SUBSTRATE FOR RELIABILITY PERFORMANCE ENHANCEMENT simplified abstract (Intel Corporation)

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SINX ADHESION PROMOTER WITH ADHESION HOLE FEATURES IN PACKAGING SUBSTRATE FOR RELIABILITY PERFORMANCE ENHANCEMENT

Organization Name

Intel Corporation

Inventor(s)

Jieying Kong of Chandler AZ (US)

Whitney Bryks of Tempe AZ (US)

Dilan Seneviratne of Chandler AZ (US)

Suddhasattwa Nad of Chandler AZ (US)

Srinivas V. Pietambaram of Chandler AZ (US)

SINX ADHESION PROMOTER WITH ADHESION HOLE FEATURES IN PACKAGING SUBSTRATE FOR RELIABILITY PERFORMANCE ENHANCEMENT - A simplified explanation of the abstract

This abstract first appeared for US patent application 17852039 titled 'SINX ADHESION PROMOTER WITH ADHESION HOLE FEATURES IN PACKAGING SUBSTRATE FOR RELIABILITY PERFORMANCE ENHANCEMENT

Simplified Explanation

The abstract describes electronic packages that consist of multiple layers and components. Here is a simplified explanation of the abstract:

  • The electronic package includes a first layer made of a dielectric material.
  • There is a trace (a conductive pathway) on the first layer.
  • A pad is present on the first layer.
  • A liner is placed over the first layer, trace, and pad, with a hole provided through the liner.
  • The electronic package also includes a second layer over the first layer, trace, pad, and liner.

Potential applications of this technology:

  • Electronic packaging for various devices such as smartphones, tablets, laptops, etc.
  • Integrated circuits and microchips.
  • Printed circuit boards (PCBs) used in electronic devices.

Problems solved by this technology:

  • Provides a multi-layer structure for electronic packages, allowing for more complex circuitry and components.
  • Offers a dielectric material layer for insulation and protection.
  • Enables the creation of conductive pathways (traces) for electrical connections.

Benefits of this technology:

  • Improved functionality and performance of electronic devices.
  • Enhanced durability and protection for circuitry.
  • Enables miniaturization and compact design of electronic packages.


Original Abstract Submitted

Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first layer, where the first layer is a dielectric material, and a trace on the first layer. In an embodiment, a pad is on the first layer, and a liner is over the first layer, the trace, and the pad, where a hole is provided through the liner. In an embodiment, the electronic package further comprises a second layer over the first layer, the trace, the pad, and the liner.