17850769. FABRICATION OF GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING COMMON METAL GATES AND HAVING GATE DIELECTRICS WITH AN OPPOSITE POLARITY DIPOLE LAYER simplified abstract (Intel Corporation)
Contents
- 1 FABRICATION OF GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING COMMON METAL GATES AND HAVING GATE DIELECTRICS WITH AN OPPOSITE POLARITY DIPOLE LAYER
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 FABRICATION OF GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING COMMON METAL GATES AND HAVING GATE DIELECTRICS WITH AN OPPOSITE POLARITY DIPOLE LAYER - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Original Abstract Submitted
FABRICATION OF GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING COMMON METAL GATES AND HAVING GATE DIELECTRICS WITH AN OPPOSITE POLARITY DIPOLE LAYER
Organization Name
Inventor(s)
Dan S. Lavric of Beaverton OR (US)
Dax M. Crum of Beaverton OR (US)
YenTing Chiu of Portland OR (US)
David J. Towner of Portland OR (US)
Tahir Ghani of Portland OR (US)
FABRICATION OF GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING COMMON METAL GATES AND HAVING GATE DIELECTRICS WITH AN OPPOSITE POLARITY DIPOLE LAYER - A simplified explanation of the abstract
This abstract first appeared for US patent application 17850769 titled 'FABRICATION OF GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING COMMON METAL GATES AND HAVING GATE DIELECTRICS WITH AN OPPOSITE POLARITY DIPOLE LAYER
Simplified Explanation
The abstract describes gate-all-around integrated circuit structures with common metal gates and gate dielectrics containing a dipole layer. The structure includes two vertical arrangements of horizontal nanowires, each with a gate stack. The first gate stack is for PMOS and includes a P-type conductive layer on a gate dielectric with an N-type dipole material layer. The second gate stack is for NMOS and also includes the P-type conductive layer on a gate dielectric with the N-type dipole material layer and an additional N-type dipole material layer.
- Gate-all-around integrated circuit structures with common metal gates and gate dielectrics containing a dipole layer
- Two vertical arrangements of horizontal nanowires with separate gate stacks for PMOS and NMOS
- PMOS gate stack includes P-type conductive layer and gate dielectric with N-type dipole material layer
- NMOS gate stack includes P-type conductive layer and gate dielectric with N-type dipole material layer and an additional N-type dipole material layer
Potential Applications
- Integrated circuits
- Semiconductor devices
Problems Solved
- Improved performance and efficiency of integrated circuits
- Enhanced control over the flow of current in PMOS and NMOS devices
Benefits
- Common metal gates simplify manufacturing processes
- Gate dielectrics with dipole layers improve device performance
- Allows for better control and optimization of PMOS and NMOS devices
Original Abstract Submitted
Gate-all-around integrated circuit structures having common metal gates and having gate dielectrics with a dipole layer are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, the first gate stack a PMOS gate stack having a P-type conductive layer on a first gate dielectric including a first N-type dipole material layer. A second gate stack is over the second vertical arrangement of horizontal nanowires, the second gate stack an NMOS gate stack having the P-type conductive layer on a second gate dielectric including the first N-type dipole material layer and a second N-type dipole material layer.
