18456699. SYSTEMS, APPARATUSES, AND METHODS FOR ADDITION OF PARTIAL PRODUCTS simplified abstract (Intel Corporation)

SYSTEMS, APPARATUSES, AND METHODS FOR ADDITION OF PARTIAL PRODUCTS

Organization Name

Intel Corporation

Inventor(s)

Robert Valentine of Kiryat Tivon (IL)

Galina Ryvchin of Haifa (IL)

Piotr Majcher of Straszyn (PL)

Mark J. Charney of Lexington MA (US)

Elmoustapha Ould-ahmed-vall of Chandler AZ (US)

Jesus Corbal of King City OR (US)

Milind B. Girkar of Sunnyvale CA (US)

Zeev Sperber of Zichron Yackov (IL)

Simon Rubanovich of Haifa (IL)

Amit Gradstein of Binyamina (IL)

SYSTEMS, APPARATUSES, AND METHODS FOR ADDITION OF PARTIAL PRODUCTS - A simplified explanation of the abstract

This abstract first appeared for US patent application 18456699 titled 'SYSTEMS, APPARATUSES, AND METHODS FOR ADDITION OF PARTIAL PRODUCTS

Simplified Explanation

The patent application describes systems, apparatuses, and methods for fused multiple add. It involves a decoder that decodes a single instruction with various fields representing operands of different sizes. The execution circuitry then performs multiplications and additions on these operands and stores the results in a destination operand.

• The patent application involves a decoder that can decode a single instruction with multiple operands of different sizes.
• The execution circuitry performs multiplications and additions on these operands.
• The results of these operations are stored in a destination operand.
• The size of the operands and the number of elements in each operand can be adjusted based on the requirements of the application.
• The technology allows for efficient processing of multiple add operations in a single instruction.

Potential Applications

• This technology can be applied in various fields that require efficient processing of multiple add operations, such as computer graphics, image processing, and scientific simulations.
• It can be used in processors and computing systems to improve performance and reduce processing time for complex calculations.
• The technology can also be utilized in artificial intelligence and machine learning applications that involve large-scale data processing.

Problems Solved

• Traditional processors often require multiple instructions to perform multiple add operations, leading to increased complexity and longer processing time.
• The patent application solves this problem by introducing a fused multiple add instruction that can perform multiple add operations in a single instruction, reducing the number of instructions and improving efficiency.
• The technology also addresses the issue of handling operands of different sizes by allowing for flexible adjustments based on the requirements of the application.

Benefits

• The fused multiple add instruction reduces the number of instructions required for multiple add operations, leading to improved performance and efficiency.
• By performing multiple add operations in a single instruction, the technology reduces the complexity of the processor and simplifies the programming process.
• The ability to handle operands of different sizes provides flexibility and adaptability to different applications and computing requirements.

Original Abstract Submitted

Embodiments of systems, apparatuses, and methods for fused multiple add. In some embodiments, a decoder decodes a single instruction having an opcode, a destination field representing a destination operand, and fields for a first, second, and third packed data source operand, wherein packed data elements of the first and second packed data source operand are of a first, different size than a second size of packed data elements of the third packed data operand. Execution circuitry then executes the decoded single instruction to perform, for each packed data element position of the destination operand, a multiplication of a M N-sized packed data elements from the first and second packed data sources that correspond to a packed data element position of the third packed data source, add of results from these multiplications to a full-sized packed data element of a packed data element position of the third packed data source, and storage of the addition result in a packed data element position destination corresponding to the packed data element position of the third packed data source, wherein M is equal to the full-sized packed data element divided by N.