17809329. DIFFUSION CUT STRESSORS FOR STACKED TRANSISTORS simplified abstract (Intel Corporation)

DIFFUSION CUT STRESSORS FOR STACKED TRANSISTORS

Organization Name

Intel Corporation

Inventor(s)

Cheng-Ying Huang of Hillsboro OR (US)

Munzarin F. Qayyum of Hillsboro OR (US)

Nicole K. Thomas of Portland OR (US)

Rohit Galatage of Hillsboro OR (US)

Patrick Morrow of Portland OR (US)

Jami A. Wiedemer of Scappoose OR (US)

Marko Radosavljevic of Portland OR (US)

Jack T. Kavalieros of Portland OR (US)

DIFFUSION CUT STRESSORS FOR STACKED TRANSISTORS - A simplified explanation of the abstract

This abstract first appeared for US patent application 17809329 titled 'DIFFUSION CUT STRESSORS FOR STACKED TRANSISTORS

Simplified Explanation

The patent application describes techniques for creating non-planar semiconductor devices in a stacked transistor configuration next to stressor materials. The configuration includes an n-channel device and a p-channel device, both of which are gate-all-around transistors with nanoribbons extending in the same direction. The n-channel device is positioned vertically above the p-channel device (or vice versa), and source or drain regions are located adjacent to both ends of each device.

• The patent application proposes a stacked transistor configuration with gate-all-around transistors.
• The configuration includes nanoribbons extending in the same direction.
• The n-channel and p-channel devices are positioned vertically above each other.
• Source or drain regions are located adjacent to both ends of each device.
• Stressor materials are used on the opposite side of the stacked source or drain regions to fill the gate trench.
• The stressor materials may include a compressive stressor material adjacent to the p-channel device and/or a tensile stressor material adjacent to the n-channel device.
• The stressor material(s) may form part of a diffusion cut structure.

Potential Applications

• Semiconductor manufacturing
• Integrated circuit design
• Transistor fabrication

Problems Solved

• Non-planar semiconductor devices can be challenging to fabricate.
• Stacked transistor configurations can introduce stress-related issues.
• Diffusion cut structures may be difficult to implement effectively.

Benefits

• Improved performance and efficiency of semiconductor devices.
• Enhanced control over stress effects in stacked transistor configurations.
• Simplified fabrication process for non-planar semiconductor devices.

Original Abstract Submitted

Techniques are provided herein to form non-planar semiconductor devices in a stacked transistor configuration adjacent to stressor materials. In one example, an n-channel device and a p-channel device may both be gate-all-around transistors each having any number of nanoribbons extending in the same direction, where the n-channel device is located vertically above the p-channel device (or vice versa). Source or drain regions are adjacent to both ends of the n-channel device and both ends of the p-channel device. On the opposite side of the stacked source or drain regions (e.g., opposite from the nanoribbons), stressor materials may be used to fill the gate trench in place of additional semiconductor devices. The stressor materials may include, for instance, a compressive stressor material adjacent to the p-channel device and/or a tensile stressor material adjacent to the n-channel device. The stressor material(s) may form or otherwise be part of a diffusion cut structure.