17846153. PACKAGE ARCHITECTURE OF THREE-DIMENSIONAL INTERCONNECT CUBE WITH INTEGRATED CIRCUIT DIES HAVING PLANARIZED EDGES simplified abstract (Intel Corporation)

PACKAGE ARCHITECTURE OF THREE-DIMENSIONAL INTERCONNECT CUBE WITH INTEGRATED CIRCUIT DIES HAVING PLANARIZED EDGES

Organization Name

Intel Corporation

Inventor(s)

Sagar Suthram of Portland OR (US)

Ravindranath Vithal Mahajan of Chandler AZ (US)

Debendra Mallik of Chandler AZ (US)

Omkar G. Karhade of Chandler AZ (US)

Wilfred Gomes of Portland OR (US)

Pushkar Sharad Ranade of San Jose CA (US)

Abhishek A. Sharma of Hillsboro OR (US)

Tahir Ghani of Portland OR (US)

Anand S. Murthy of Portland OR (US)

Nitin A. Deshpande of Chandler AZ (US)

Joshua Fryman of Corvallis OR (US)

Stephen Morein of San Jose CA (US)

Matthew Adiletta of Bolton MA (US)

PACKAGE ARCHITECTURE OF THREE-DIMENSIONAL INTERCONNECT CUBE WITH INTEGRATED CIRCUIT DIES HAVING PLANARIZED EDGES - A simplified explanation of the abstract

This abstract first appeared for US patent application 17846153 titled 'PACKAGE ARCHITECTURE OF THREE-DIMENSIONAL INTERCONNECT CUBE WITH INTEGRATED CIRCUIT DIES HAVING PLANARIZED EDGES

Simplified Explanation

The abstract describes embodiments of an integrated circuit (IC) die that includes a metallization stack and a substrate. The metallization stack consists of a dielectric material, multiple layers of conductive traces, and conductive vias. The substrate is attached to the metallization stack along a planar interface. The metallization stack also includes bond-pads on different surfaces.

• The IC die includes a metallization stack with conductive traces and vias, and a substrate.
• The metallization stack is made up of a dielectric material and multiple layers of conductive traces.
• The substrate is attached to the metallization stack along a planar interface.
• The metallization stack has bond-pads on different surfaces, including the first, second, third, fourth, and fifth surfaces.
• The first surface is parallel to the planar interface, while the second and third surfaces are parallel to each other and orthogonal to the first surface.
• The fourth and fifth surfaces are parallel to each other and orthogonal to both the first and second surfaces.

Potential applications of this technology:

• Integrated circuits and microchips
• Electronic devices and systems
• Semiconductor manufacturing

Problems solved by this technology:

• Efficient integration of conductive traces and vias in an IC die
• Improved connectivity and signal transmission within the IC die

Benefits of this technology:

• Enhanced performance and functionality of integrated circuits
• Increased reliability and durability of electronic devices
• Simplified manufacturing processes for semiconductor devices

Original Abstract Submitted

Embodiments of an integrated circuit (IC) die comprise: a metallization stack including a dielectric material, a plurality of layers of conductive traces in the dielectric material and conductive vias through the dielectric material; and a substrate attached to the metallization stack along a planar interface. The metallization stack comprises bond-pads on a first surface, a second surface, a third surface, a fourth surface, and a fifth surface. The first surface is parallel to the planar interface between the metallization stack and the substrate, the second surface is parallel to the third surface and orthogonal to the first surface, and the fourth surface is parallel to the fifth surface and orthogonal to the first surface and the second surface.