17847652. STRESS-REDUCING DIELECTRIC-TO-METAL ADHESION ARCHITECTURE FOR ELECTRONIC PACKAGES simplified abstract (Intel Corporation)

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STRESS-REDUCING DIELECTRIC-TO-METAL ADHESION ARCHITECTURE FOR ELECTRONIC PACKAGES

Organization Name

Intel Corporation

Inventor(s)

Yi Yang of Gilbert AZ (US)

Srinivas Pietambaram of Chandler AZ (US)

Suddhasattwa Nad of Chandler AZ (US)

STRESS-REDUCING DIELECTRIC-TO-METAL ADHESION ARCHITECTURE FOR ELECTRONIC PACKAGES - A simplified explanation of the abstract

This abstract first appeared for US patent application 17847652 titled 'STRESS-REDUCING DIELECTRIC-TO-METAL ADHESION ARCHITECTURE FOR ELECTRONIC PACKAGES

Simplified Explanation

The abstract describes an electronic device package that includes multiple layers of different materials to enhance its functionality and performance.

  • The package substrate has a conductive feature that connects to an integrated circuit die.
  • The first dielectric layer, made of silicon and nitrogen, is applied over the conductive feature.
  • A second dielectric layer, also made of silicon and nitrogen, is added on top of the first layer with a different thickness.
  • Finally, a third dielectric layer made of an organic material is applied over the second layer.

Potential applications of this technology:

  • Electronic devices such as smartphones, tablets, and computers.
  • Integrated circuits and microchips used in various industries.

Problems solved by this technology:

  • Enhances the conductivity and performance of the electronic device package.
  • Provides better insulation and protection for the integrated circuit die.

Benefits of this technology:

  • Improved functionality and performance of electronic devices.
  • Enhanced durability and protection for integrated circuits.
  • Increased efficiency and reliability of electronic device packages.


Original Abstract Submitted

An electronic device package comprises a conductive feature over a first surface of a package substrate, the conductive feature to couple to an integrated circuit die; a first dielectric layer on the conductive feature, the first dielectric layer having a first thickness and comprising silicon and nitrogen; a second dielectric layer over the first dielectric layer and having a second thickness different than the first thickness and comprising silicon and nitrogen; and a third dielectric layer over the second dielectric layer and comprising an organic material.

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