18207870. SYSTEMS, METHODS, AND APPARATUSES FOR HETEROGENEOUS COMPUTING simplified abstract (Intel Corporation)

SYSTEMS, METHODS, AND APPARATUSES FOR HETEROGENEOUS COMPUTING

Organization Name

Intel Corporation

Inventor(s)

Rajesh M. Sankaran of Portland OR (US)

Gilbert Neiger of Hillsboro OR (US)

Narayan Ranganathan of Bangalore (IN)

Stephen R. Van Doren of Portland OR (US)

Joseph Nuzman of Haifa (IL)

Niall D. Mcdonnell of Limerick (IE)

Michael A. O'hanlon of Limerick (IE)

Lokpraveen B. Mosur of Gilbert AZ (US)

Tracy Garrett Drysdale of Paradise Valley AZ (US)

Eriko Nurvitadhi of Hillsboro OR (US)

Asit K. Mishra of Hillsboro OR (US)

Ganesh Venkatesh of Hillsboro OR (US)

Deborah T. Marr of Portland OR (US)

Nicholas P. Carter of Somerville MA (US)

Jonathan D. Pearce of Hillsboro OR (US)

Edward T. Grochowski of San Jose CA (US)

Richard J. Greco of Hillsboro OR (US)

Robert Valentine of Kiryat Tivon (IL)

Jesus Corbal of King City OR (US)

Thomas D. Fletcher of Sherwood OR (US)

Dennis R. Bradford of Portland OR (US)

Dwight P. Manley of Holliston MA (US)

Mark J. Charney of Lexington MA (US)

Jeffrey J. Cook of Portland OR (US)

Paul Caprioli of Hillsboro OR (US)

Koichi Yamada of Los Gatos CA (US)

Kent D. Glossop of Merrimack NH (US)

David B. Sheffield of Hillsboro OR (US)

SYSTEMS, METHODS, AND APPARATUSES FOR HETEROGENEOUS COMPUTING - A simplified explanation of the abstract

This abstract first appeared for US patent application 18207870 titled 'SYSTEMS, METHODS, AND APPARATUSES FOR HETEROGENEOUS COMPUTING

Simplified Explanation

The abstract describes a patent application related to heterogeneous computing, specifically focusing on a hardware heterogeneous scheduler that dispatches instructions for execution on multiple heterogeneous processing elements. The instructions are native instructions specific to the processing elements.

• The patent application is about systems, methods, and apparatuses for heterogeneous computing.
• It introduces a hardware heterogeneous scheduler that dispatches instructions for execution on multiple heterogeneous processing elements.
• The instructions correspond to a code fragment that needs to be processed by the processing elements.
• The instructions are native instructions specific to at least one of the processing elements.

Potential Applications

• High-performance computing: This technology can be applied in fields that require intensive computational tasks, such as scientific simulations, data analysis, and machine learning.
• Graphics processing: The heterogeneous computing approach can enhance graphics processing capabilities, enabling more realistic and immersive visual experiences in applications like gaming and virtual reality.
• Mobile devices: Heterogeneous computing can improve the performance and efficiency of mobile devices, allowing for better multitasking, faster app execution, and longer battery life.

Problems Solved

• Efficient utilization of heterogeneous processing elements: The hardware heterogeneous scheduler ensures that instructions are dispatched to the appropriate processing elements, maximizing their capabilities and optimizing overall system performance.
• Native instruction execution: By utilizing native instructions specific to each processing element, the technology eliminates the need for translation or interpretation, reducing processing overhead and improving efficiency.

Benefits

• Improved performance: By effectively utilizing multiple heterogeneous processing elements, the technology can significantly enhance computational performance, enabling faster and more complex computations.
• Enhanced efficiency: The hardware heterogeneous scheduler and native instruction execution minimize processing overhead, leading to improved energy efficiency and reduced power consumption.
• Versatility: The technology supports a wide range of applications and can be implemented in various computing systems, including high-performance servers, mobile devices, and embedded systems.

Original Abstract Submitted

Embodiments of systems, methods, and apparatuses for heterogeneous computing are described. In some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more plurality of heterogeneous processing elements, the instructions corresponding to a code fragment to be processed by the one or more of the plurality of heterogeneous processing elements, wherein the instructions are native instructions to at least one of the one or more of the plurality of heterogeneous processing elements.