17851960. INTEGRATED CIRCUIT STRUCTURES HAVING AOI GATES WITH ROUTING ACROSS NANOWIRES simplified abstract (Intel Corporation)
INTEGRATED CIRCUIT STRUCTURES HAVING AOI GATES WITH ROUTING ACROSS NANOWIRES
Organization Name
Inventor(s)
Abhishek Anil Sharma of Portland OR (US)
Wilfred Gomes of Portland OR (US)
Anand S. Murthy of Portland OR (US)
Tahir Ghani of Portland OR (US)
Sagar Suthram of Portland OR (US)
INTEGRATED CIRCUIT STRUCTURES HAVING AOI GATES WITH ROUTING ACROSS NANOWIRES - A simplified explanation of the abstract
This abstract first appeared for US patent application 17851960 titled 'INTEGRATED CIRCUIT STRUCTURES HAVING AOI GATES WITH ROUTING ACROSS NANOWIRES
Simplified Explanation
The patent application describes a structure for integrated circuits that includes nanowires and gate stacks with cuts in a vertical direction.
- The structure includes a stack of horizontal nanowires arranged vertically.
- A gate stack is placed over the horizontal nanowires, surrounding the channel region of each wire.
- The gate stack has one or more cuts in the vertical direction.
Potential Applications
This technology has potential applications in various fields, including:
- Integrated circuit manufacturing
- Nanoelectronics
- Semiconductor industry
Problems Solved
The technology addresses the following problems:
- Efficient routing of signals across nanowires in integrated circuits
- Enhancing the performance and functionality of integrated circuits
- Overcoming limitations in traditional gate stack designs
Benefits
The technology offers several benefits, including:
- Improved signal routing capabilities across nanowires
- Enhanced performance and functionality of integrated circuits
- Increased efficiency in integrated circuit manufacturing processes
Original Abstract Submitted
Structures having AOI gates with routing across nanowires are described. In an example, an integrated circuit structure includes a stack of horizontal nanowires along a vertical direction. A gate stack is over the stack of horizontal nanowires and is surrounding a channel region of each of the horizontal nanowires, the gate stack having one or more cuts in the vertical direction.
