17850044. RECONFIGURABLE VECTOR PROCESSING IN A MEMORY simplified abstract (Intel Corporation)

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RECONFIGURABLE VECTOR PROCESSING IN A MEMORY

Organization Name

Intel Corporation

Inventor(s)

Abhishek Anil Sharma of Portland OR (US)

Pushkar Ranade of San Jose CA (US)

Wilfred Gomes of Portland OR (US)

Sagar Suthram of Portland OR (US)

RECONFIGURABLE VECTOR PROCESSING IN A MEMORY - A simplified explanation of the abstract

This abstract first appeared for US patent application 17850044 titled 'RECONFIGURABLE VECTOR PROCESSING IN A MEMORY

Simplified Explanation

The abstract of this patent application describes a memory system that includes a die with multiple memory layers and at least one reconfigurable vector processor. The reconfigurable vector processor performs vector computations on input vector data obtained from the memory banks and provides processed vector data back to the memory banks.

  • The memory system includes multiple memory layers with banks to store data.
  • The memory system also includes at least one reconfigurable vector processor.
  • The reconfigurable vector processor performs vector computations on input vector data.
  • The input vector data is obtained from the memory banks.
  • The processed vector data is provided back to the memory banks.

Potential applications of this technology:

  • High-performance computing systems
  • Artificial intelligence and machine learning applications
  • Data-intensive applications requiring efficient processing of large datasets

Problems solved by this technology:

  • Improved memory system performance by integrating a reconfigurable vector processor
  • Efficient processing of vector computations on data stored in memory banks

Benefits of this technology:

  • Faster and more efficient processing of vector computations
  • Reduced data transfer between memory and processing units
  • Improved overall system performance and energy efficiency


Original Abstract Submitted

In one embodiment, a memory includes a die having: one or more memory layers having a plurality of banks to store data; and at least one other layer comprising at least one reconfigurable vector processor, the at least one reconfigurable vector processor to perform a vector computation on input vector data obtained from at least one bank of the plurality of banks and provide processed vector data to the at least one bank. Other embodiments are described and claimed.

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