17846086. PACKAGE ARCHITECTURE WITH VERTICAL STACKING OF INTEGRATED CIRCUIT DIES HAVING PLANARIZED EDGES simplified abstract (Intel Corporation)

PACKAGE ARCHITECTURE WITH VERTICAL STACKING OF INTEGRATED CIRCUIT DIES HAVING PLANARIZED EDGES

Organization Name

Intel Corporation

Inventor(s)

Sagar Suthram of Portland OR (US)

Omkar G. Karhade of Chandler AZ (US)

Ravindranath Vithal Mahajan of Chandler AZ (US)

Debendra Mallik of Chandler AZ (US)

Nitin A. Deshpande of Chandler AZ (US)

Pushkar Sharad Ranade of San Jose CA (US)

Wilfred Gomes of Portland OR (US)

Abhishek A. Sharma of Hillsboro OR (US)

Tahir Ghani of Portland OR (US)

Anand S. Murthy of Portland OR (US)

Joshua Fryman of Corvallis OR (US)

Stephen Morein of San Jose CA (US)

Matthew Adiletta of Bolton MA (US)

Michael Crocker of Portland OR (US)

Aaron Gorius of Upton MA (US)

PACKAGE ARCHITECTURE WITH VERTICAL STACKING OF INTEGRATED CIRCUIT DIES HAVING PLANARIZED EDGES - A simplified explanation of the abstract

This abstract first appeared for US patent application 17846086 titled 'PACKAGE ARCHITECTURE WITH VERTICAL STACKING OF INTEGRATED CIRCUIT DIES HAVING PLANARIZED EDGES

Simplified Explanation

The abstract describes embodiments of an integrated circuit (IC) die that consist of two regions: a first region and a second region. The first region has two surfaces, with one surface perpendicular to the other. The second region is attached to the first region along a planar interface that is perpendicular to the first surface and parallel to the second surface. The second region has a surface that is coplanar with the first surface.

• The first region of the IC die is made of a dielectric material.
• The first region contains layers of conductive traces embedded in the dielectric material. Each layer of conductive traces is parallel to the second surface, and the traces are perpendicular to the first surface.
• The first region also includes conductive vias that pass through the dielectric material.
• The first surface of the first region has bond-pads, which are exposed portions of the conductive traces.
• The second region of the IC die is made of a material different from the dielectric material.

Potential Applications

• Integrated circuits and microchips
• Electronic devices and gadgets
• Communication systems and networks

Problems Solved

• Provides a structure for integrating different materials in an IC die
• Enables efficient routing of conductive traces in the dielectric material
• Facilitates the connection of external devices to the IC die through bond-pads

Benefits

• Enhanced performance and functionality of integrated circuits
• Improved reliability and durability of IC dies
• Enables miniaturization and compactness of electronic devices

Original Abstract Submitted

Embodiments of an integrated circuit (IC) die comprise: a first region having a first surface and a second surface, the first surface being orthogonal to the second surface; and a second region attached to the first region along a planar interface that is orthogonal to the first surface and parallel to the second surface, the second region having a third surface coplanar with the first surface. The first region comprises: a dielectric material; layers of conductive traces in the dielectric material, each layer of the conductive traces being parallel to the second surface such that the conductive traces are orthogonal to the first surface; conductive vias through the dielectric material; and bond-pads on the first surface, the bond-pads comprising portions of the conductive traces exposed on the first surface, and the second region comprises a material different from the dielectric material.