17847628. LOWER DEVICE ACCESS IN STACKED TRANSISTOR DEVICES simplified abstract (Intel Corporation)

LOWER DEVICE ACCESS IN STACKED TRANSISTOR DEVICES

Organization Name

Intel Corporation

Inventor(s)

Cheng-Ying Huang of Hillsboro OR (US)

Patrick Morrow of Portland OR (US)

Quan Shi of Portland OR (US)

Rohit Galatage of Hillsboro OR (US)

Nicole K. Thomas of Portland OR (US)

Munzarin F. Qayyum of Hillsboro OR (US)

Jami A. Wiedemer of Scappoose OR (US)

Gilbert Dewey of Beaverton OR (US)

Mauro J. Kobrinsky of Portland OR (US)

Marko Radosavljevic of Portland OR (US)

Jack T. Kavalieros of Portland OR (US)

LOWER DEVICE ACCESS IN STACKED TRANSISTOR DEVICES - A simplified explanation of the abstract

This abstract first appeared for US patent application 17847628 titled 'LOWER DEVICE ACCESS IN STACKED TRANSISTOR DEVICES

Simplified Explanation

The patent application describes an integrated circuit structure that includes a device layer with an upper device and a lower device. The upper device has an upper source or drain region and an upper source or drain contact, while the lower device has a lower source or drain region.

• The integrated circuit structure includes a first conductive feature below the device layer, which is connected to the lower source or drain region.
• A second conductive feature vertically extends through the device layer and connects the first conductive feature below the device layer to an interconnect structure above the device layer.
• This arrangement allows for a connection between the interconnect structure on the frontside of the integrated circuit and the lower source or drain region towards the backside of the integrated circuit.

Potential applications of this technology:

• This integrated circuit structure can be used in various electronic devices, such as smartphones, computers, and IoT devices.
• It can be applied in the manufacturing of advanced semiconductor chips for improved performance and functionality.

Problems solved by this technology:

• The integration of the first and second conductive features enables a more efficient and compact design of the integrated circuit structure.
• It provides a reliable connection between the interconnect structure and the lower source or drain region, improving overall circuit performance.

Benefits of this technology:

• The integrated circuit structure allows for better signal transmission and reduced power consumption.
• It enables higher integration density and improved functionality in electronic devices.
• The design simplifies the manufacturing process and reduces production costs.

Original Abstract Submitted

An integrated circuit structure includes a device layer including an upper device above a lower device. The upper device includes an upper source or drain region, and an upper source or drain contact coupled to the upper source or drain region. The lower device includes a lower source or drain region. A first conductive feature is below the device layer, where the first conductive feature is coupled to the lower source or drain region. A second conductive feature vertically extends through the device layer. In an example, the second conductive feature is to couple (i) the first conductive feature below the device layer and (ii) an interconnect structure above the device layer. Thus, the first and second conductive features facilitate a connection between the interconnect structure on the frontside of the integrated circuit and the lower source or drain region towards the backside of the integrated circuit.