18243896. PACKET PROCESSING WITH REDUCED LATENCY simplified abstract (Intel Corporation)

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PACKET PROCESSING WITH REDUCED LATENCY

Organization Name

Intel Corporation

Inventor(s)

Eliezer Tamir of Bait Shemesh (IL)

Jesse C. Brandeburg of Portland OR (US)

Anil Vasudevan of Portland OR (US)

PACKET PROCESSING WITH REDUCED LATENCY - A simplified explanation of the abstract

This abstract first appeared for US patent application 18243896 titled 'PACKET PROCESSING WITH REDUCED LATENCY

Simplified Explanation

Abstract

This patent application describes a technology for packet processing with reduced latency. It introduces a device that includes a data queue, an interrupt generation circuit, and an interrupt delay register.

  • The device has a data queue to store data descriptors associated with data packets.
  • The data packets are transferred between a network and a driver circuit.
  • An interrupt generation circuit is included to generate an interrupt to the driver circuit.
  • The interrupt is generated when a delay timer expires and the data queue is not empty.
  • An interrupt delay register enables the driver circuit to reset the delay timer, postponing the interrupt generation.

Potential Applications

  • Network devices and routers that require efficient packet processing.
  • Real-time applications that demand low latency, such as video streaming or online gaming.
  • Cloud computing infrastructure to optimize data transfer between servers.

Problems Solved

  • Reduces latency in packet processing, improving overall network performance.
  • Ensures timely processing of data packets, minimizing delays and improving user experience.
  • Optimizes the utilization of network resources by efficiently managing data queues.

Benefits

  • Reduced latency in packet processing, leading to faster data transfer and improved network performance.
  • Enhanced user experience in real-time applications with reduced delays.
  • Efficient utilization of network resources, improving overall network efficiency.


Original Abstract Submitted

Generally, this disclosure provides devices, methods, and computer readable media for packet processing with reduced latency. The device may include a data queue to store data descriptors associated with data packets, the data packets to be transferred between a network and a driver circuit. The device may also include an interrupt generation circuit to generate an interrupt to the driver circuit. The interrupt may be generated in response to a combination of an expiration of a delay timer and a non-empty condition of the data queue. The device may further include an interrupt delay register to enable the driver circuit to reset the delay timer, the reset postponing the interrupt generation.

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