18367292. GATE CUT AND FIN TRIM ISOLATION FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION simplified abstract (Intel Corporation)

GATE CUT AND FIN TRIM ISOLATION FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION

Organization Name

Intel Corporation

Inventor(s)

Tahir Ghani of Portland OR (US)

Byron Ho of Hillsboro OR (US)

Michael L. Hattendorf of Portland OR (US)

Christopher P. Auth of Portland OR (US)

GATE CUT AND FIN TRIM ISOLATION FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION - A simplified explanation of the abstract

This abstract first appeared for US patent application 18367292 titled 'GATE CUT AND FIN TRIM ISOLATION FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION

Abstract Explanation

This patent application is related to the fabrication of advanced integrated circuit structures, specifically those with a size of 10 nanometers or smaller. The method described involves forming multiple fins and gate structures over these fins. A dielectric material structure is then formed between the gate structures. Portions of the gate structures are removed to expose different portions of the fins. The exposed first portion of each fin is removed, while the exposed second portion is not removed.

Bullet Points

• The patent application is about a method for fabricating advanced integrated circuit structures.
• It specifically focuses on structures with a size of 10 nanometers or smaller.
• The method involves forming multiple fins and gate structures over these fins.
• A dielectric material structure is formed between the gate structures.
• Portions of the gate structures are removed to expose different portions of the fins.
• The exposed first portion of each fin is removed, while the exposed second portion is not removed.

Potential Applications

• This technology can be applied in the fabrication of advanced integrated circuits with a size of 10 nanometers or smaller.
• It can be used in the production of high-performance electronic devices, such as smartphones, tablets, and computers.
• The method described in the patent application can enable the creation of more compact and efficient integrated circuit structures.

Problems Solved

• The method addresses the challenge of fabricating integrated circuit structures with a size of 10 nanometers or smaller.
• It solves the problem of exposing different portions of the fins while maintaining the desired structure.
• The method provides a solution for removing specific portions of the gate structures to achieve the desired circuit configuration.

Benefits

• The technology allows for the fabrication of advanced integrated circuits with improved performance and efficiency.
• It enables the creation of smaller and more compact electronic devices.
• The method described in the patent application offers a precise and controlled approach to fabricating integrated circuit structures.

Original Abstract Submitted

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, a method includes forming a plurality of fins and forming a plurality of gate structures over the plurality of fins. A dielectric material structure is formed between adjacent ones of the plurality of gate structures. A portion of a first of the plurality of gate structures is removed to expose a first portion of each of the plurality of fins, and a portion of a second of the plurality of gate structures is removed to expose a second portion of each of the plurality of fins. The exposed first portion of each of the plurality of fins is removed, but the exposed second portion of each of the plurality of fins is not removed.