18367319. LARGE GRAIN AND HALOGEN-FREE SILICON CELL CHANNEL FOR 3D NAND STRING simplified abstract (Intel Corporation)

LARGE GRAIN AND HALOGEN-FREE SILICON CELL CHANNEL FOR 3D NAND STRING

Organization Name

Intel Corporation

Inventor(s)

Jessica S. Kachian of Half Moon Bay CA (US)

LARGE GRAIN AND HALOGEN-FREE SILICON CELL CHANNEL FOR 3D NAND STRING - A simplified explanation of the abstract

This abstract first appeared for US patent application 18367319 titled 'LARGE GRAIN AND HALOGEN-FREE SILICON CELL CHANNEL FOR 3D NAND STRING

Simplified Explanation

The abstract of the patent application describes an apparatus that includes an array of linear cell channels and a string of NAND memory cells arranged along a cell channel. The apparatus utilizes a polysilicon cell channel layer with specific characteristics, such as a low halogen atom count, a thin thickness, and a high grain height mean.

• The apparatus includes an array of linear cell channels and a string of NAND memory cells.
• The cell channels are made of a polysilicon layer with less than E17 halogen atoms per cubic centimeter.
• The thickness of the polysilicon layer is equal to or less than 25 nanometers.
• The polysilicon layer has an area-weighted grain height mean greater than 30 nanometers.

Potential Applications:

• This technology can be applied in the field of memory devices, specifically NAND memory cells.
• It can be used in various electronic devices, such as smartphones, tablets, and computers, to enhance memory storage capabilities.

Problems Solved:

• The use of a low halogen atom count in the polysilicon layer reduces potential harmful effects and improves the overall safety of the apparatus.
• The thin thickness of the polysilicon layer allows for more compact and efficient memory cell designs.
• The high grain height mean of the polysilicon layer enhances the performance and reliability of the memory cells.

Benefits:

• The low halogen atom count improves the safety and environmental impact of the apparatus.
• The thin polysilicon layer enables smaller and more efficient memory cell designs, leading to space-saving benefits in electronic devices.
• The high grain height mean enhances the performance and reliability of the memory cells, resulting in improved data storage and retrieval capabilities.

Original Abstract Submitted

An example of an apparatus may include an array of linear cell channels and a string of NAND memory cells arranged along a cell channel of the array of linear cell channels, where a polysilicon cell channel layer comprises material with less than E17 halogen atoms per cubic centimeter, where a thickness of the polysilicon cell channel layer is less than or equal to 25 nanometers, and where an area-weighted grain height mean of the polysilicon cell channel layer is greater than 30 nanometers. Other examples are disclosed and claimed.