17850078. SELF-ASSEMBLED MONOLAYER ON A DIELECTRIC FOR TRANSITION METAL DICHALCOGENIDE GROWTH FOR STACKED 2D CHANNELS simplified abstract (Intel Corporation)

SELF-ASSEMBLED MONOLAYER ON A DIELECTRIC FOR TRANSITION METAL DICHALCOGENIDE GROWTH FOR STACKED 2D CHANNELS

Organization Name

Intel Corporation

Inventor(s)

Carl H. Naylor of Portland OR (US)

Kirby Maxey of Hillsboro OR (US)

Kevin P. O'brien of Portland OR (US)

Chelsey Dorow of Portland OR (US)

Sudarat Lee of Hillsboro OR (US)

Ashish Verma Penumatcha of Beaverton OR (US)

Uygar E. Avci of Portland OR (US)

Matthew V. Metz of Portland OR (US)

Scott B. Clendenning of Portland OR (US)

Jiun-Ruey Chen of Hillsboro OR (US)

Chia-Ching Lin of Portland OR (US)

Carly Rogan of North Plains OR (US)

SELF-ASSEMBLED MONOLAYER ON A DIELECTRIC FOR TRANSITION METAL DICHALCOGENIDE GROWTH FOR STACKED 2D CHANNELS - A simplified explanation of the abstract

This abstract first appeared for US patent application 17850078 titled 'SELF-ASSEMBLED MONOLAYER ON A DIELECTRIC FOR TRANSITION METAL DICHALCOGENIDE GROWTH FOR STACKED 2D CHANNELS

Simplified Explanation

The abstract describes a patent application related to creating a transistor structure by selectively growing a 2D TMD (Transition Metal Dichalcogenide) directly in a stacked channel configuration, such as a stacked nanowire or nanoribbon formation. The growth of TMD occurs for all the nanowires or nanoribbons in the transistor structure in one stage. The use of a self-assembled monolayer (SAM) on multiple dielectric layers facilitates channel deposition and geometry in the stacked channel configuration.

• Selective growth of a 2D TMD directly in a stacked channel configuration
• Growth of TMD occurs for all nanowires or nanoribbons in the transistor structure in one stage
• Use of a self-assembled monolayer (SAM) on multiple dielectric layers facilitates channel deposition and geometry in the stacked channel configuration

Potential Applications

• Transistor manufacturing
• Semiconductor industry
• Electronics manufacturing

Problems Solved

• Simplifies the process of creating a transistor structure by growing a 2D TMD directly in a stacked channel configuration
• Enables simultaneous growth of TMD for all nanowires or nanoribbons in the transistor structure
• Facilitates channel deposition and geometry in the stacked channel configuration

Benefits

• Streamlines transistor manufacturing process
• Increases efficiency and speed of transistor production
• Enables the creation of more compact and advanced transistor structures

Original Abstract Submitted

Embodiments described herein may be related to apparatuses, processes, and techniques directed to creating a transistor structure by selectively growing a 2D TMD directly in a stacked channel configuration, such as a stacked nanowire or nanoribbon formation. In embodiments, this TMD growth may occur for all of the nanowires or nanoribbons in the transistor structure in one stage. Placement of a SAM on a plurality of dielectric layers within the transistor structure stack facilitates channel deposition and channel geometry in the stacked channel configuration. Other embodiments may be described and/or claimed.