17848059. INTEGRATED CIRCUIT PACKAGE WITH PSEUDO-STRIPLINE ARCHITECTURE simplified abstract (Intel Corporation)
INTEGRATED CIRCUIT PACKAGE WITH PSEUDO-STRIPLINE ARCHITECTURE
Organization Name
Inventor(s)
Eng Huat Goh of Ayer Itam (MY)
Hazwani Jaffar of Kepala Batas (MY)
Yean Ling Soon of Butterworth (MY)
INTEGRATED CIRCUIT PACKAGE WITH PSEUDO-STRIPLINE ARCHITECTURE - A simplified explanation of the abstract
This abstract first appeared for US patent application 17848059 titled 'INTEGRATED CIRCUIT PACKAGE WITH PSEUDO-STRIPLINE ARCHITECTURE
Simplified Explanation
The abstract describes a patent application for a method of routing IC device packages using a pseudo-stripline architecture. This architecture includes a separate routing structure that helps create a stripline structure within the package substrate, resulting in improved EMI performance.
- The patent application proposes a method of routing IC device packages using a pseudo-stripline architecture.
- The stripline structure is created, in part, by a routing structure separate from the package substrate's routing.
- A metallization feature within the redistribution layer (RDL) of the routing structure helps shield the signal route within the top metallization level of the package substrate.
- This method allows for fewer levels of metallization, reduced thickness, and lower cost for the package substrate.
- Despite these cost-saving measures, the IC device package still offers excellent EMI performance.
Potential Applications
This technology can be applied in various industries and applications, including:
- Electronics manufacturing
- Semiconductor packaging
- Integrated circuit design
- Telecommunications
- Consumer electronics
Problems Solved
The patent application addresses the following problems:
- Electromagnetic interference (EMI) in IC device packages
- Cost and complexity associated with multiple levels of metallization in package substrates
- Limited options for reducing package substrate thickness without compromising EMI performance
Benefits
The proposed technology offers several benefits:
- Improved EMI performance in IC device packages
- Reduced cost and complexity by using fewer levels of metallization in the package substrate
- Thinner package substrates without sacrificing EMI performance
- Enhanced signal integrity and reliability in IC chip routing
Original Abstract Submitted
IC device package routing with metallization features comprising a pseudo-stripline architecture in which the stripline structure is provisioned, in part, by a routing structure separate from routing within the package substrate. A signal route within top metallization level of a package substrate may be electrically shielded, in part, with a metallization feature within a redistribution layer (RDL) of a routing structure that couples one or more IC chips to the package substrate. Accordingly, a package substrate may have fewer levels of metallization, reduced thickness, and/or lower cost while the IC device package still offers excellent EMI performance.
