17852189. HIERARCHICAL CORE VALID TRACKER FOR CACHE COHERENCY simplified abstract (Intel Corporation)
HIERARCHICAL CORE VALID TRACKER FOR CACHE COHERENCY
Organization Name
Inventor(s)
Yedidya Hilewitz of Sharon MA (US)
Monam Agarwal of Lynnwood WA (US)
Yen-Cheng Liu of Portland OR (US)
Alexander Heinecke of San Jose CA (US)
HIERARCHICAL CORE VALID TRACKER FOR CACHE COHERENCY - A simplified explanation of the abstract
This abstract first appeared for US patent application 17852189 titled 'HIERARCHICAL CORE VALID TRACKER FOR CACHE COHERENCY
Simplified Explanation
The abstract describes techniques for hierarchical core valid tracking in a computer system.
- The patent application describes an apparatus that includes a cache to store information accessible by multiple cores.
- The apparatus also includes circuitry to maintain coherence of the information stored in the cache and to track the associations of the information with the cores in a hierarchical manner.
- The hierarchical tracking allows for the identification of a particular core based on the lowest hierarchical level.
- The patent application provides examples and claims for other variations of the techniques.
Potential Applications
- This technology can be applied in multi-core processors and computer systems where multiple cores need to access and share information.
- It can be used in high-performance computing systems, servers, and data centers to improve the efficiency and performance of data sharing between cores.
Problems Solved
- Hierarchical core valid tracking solves the problem of maintaining coherence and consistency of shared information in multi-core systems.
- It addresses the challenge of efficiently tracking associations between information and cores in a hierarchical manner.
Benefits
- The techniques described in the patent application improve the efficiency and performance of data sharing between cores.
- They ensure the coherence and consistency of shared information, reducing the risk of data corruption or inconsistencies.
- The hierarchical tracking allows for efficient identification of the core associated with a particular piece of information.
Original Abstract Submitted
Techniques for hierarchical core valid tracking are described. An example apparatus comprises a cache to store information accessible by two or more cores, and circuitry coupled to the cache to maintain coherence of the information stored in the cache and to hierarchically track respective associations of the information stored in the cache with the two or more cores, where a lowest hierarchical level of the hierarchically tracked associations is to indicate a logical core identifier of a particular core of the two or more cores. Other examples are disclosed and claimed.
