17846129. PACKAGE ARCHITECTURE WITH VERTICALLY STACKED BRIDGE DIES HAVING PLANARIZED EDGES simplified abstract (Intel Corporation)

PACKAGE ARCHITECTURE WITH VERTICALLY STACKED BRIDGE DIES HAVING PLANARIZED EDGES

Organization Name

Intel Corporation

Inventor(s)

Sagar Suthram of Portland OR (US)

Ravindranath Vithal Mahajan of Chandler AZ (US)

Debendra Mallik of Chandler AZ (US)

Omkar G. Karhade of Chandler AZ (US)

Wilfred Gomes of Portland OR (US)

Pushkar Sharad Ranade of San Jose CA (US)

Abhishek A. Sharma of Hillsboro OR (US)

Tahir Ghani of Portland OR (US)

Anand S. Murthy of Portland OR (US)

Nitin A. Deshpande of Chandler AZ (US)

PACKAGE ARCHITECTURE WITH VERTICALLY STACKED BRIDGE DIES HAVING PLANARIZED EDGES - A simplified explanation of the abstract

This abstract first appeared for US patent application 17846129 titled 'PACKAGE ARCHITECTURE WITH VERTICALLY STACKED BRIDGE DIES HAVING PLANARIZED EDGES

Simplified Explanation

The abstract describes embodiments of an integrated circuit (IC) die that consists of multiple IC dies connected through interconnects. The interconnects are located on the first surface of the first IC die and the second surfaces of the second IC dies, allowing for contact between the two surfaces. The interconnects are made up of dielectric-dielectric bonds and metal-metal bonds, with first bond-pads in the first IC die and second bond-pads in the second IC dies. The first IC die includes a substrate attached to a metallization stack, which is a series of conductive traces in a dielectric material. The first bond-pads are exposed portions of the conductive traces on the first surface.

• The patent application describes an integrated circuit die that connects multiple IC dies through interconnects.
• The interconnects are located on the first surface of the first IC die and the second surfaces of the second IC dies.
• The interconnects consist of dielectric-dielectric bonds and metal-metal bonds.
• The first IC die includes a substrate and a metallization stack, which is a series of conductive traces in a dielectric material.
• The first bond-pads are exposed portions of the conductive traces on the first surface.

Potential Applications

This technology has potential applications in various fields, including:

• Electronics manufacturing
• Semiconductor industry
• Integrated circuit design

Problems Solved

This technology addresses the following problems:

• Efficiently connecting multiple IC dies in an integrated circuit
• Ensuring reliable and robust interconnects between IC dies
• Facilitating communication and data transfer between IC dies

Benefits

The benefits of this technology include:

• Improved integration and connectivity of IC dies
• Enhanced performance and functionality of integrated circuits
• Increased reliability and durability of interconnects

Original Abstract Submitted

Embodiments of an integrated circuit (IC) die comprise: a first IC die coupled to at least two second IC dies by interconnects on a first surface of the first IC die and second surfaces of the second IC dies such that the first surface is in contact with the second surfaces. The second surfaces are coplanar, the interconnects comprise dielectric-dielectric bonds and metal-metal bonds, the metal-metal bonds include first bond-pads in the first IC die and second bond-pads in the second IC dies, the first IC die comprises a substrate attached to a metallization stack along a planar interface that is orthogonal to the first surface, the metallization stack comprises a plurality of layers of conductive traces in a dielectric material, and the first bond-pads comprise portions of the conductive traces exposed on the first surface.