Difference between revisions of "Samsung Electronics Co., Ltd. patent applications published on November 2nd, 2023"

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'''Summary of the patent applications from Samsung Electronics Co., Ltd. on November 2nd, 2023'''
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Samsung Electronics Co., Ltd. has recently filed several patents related to semiconductor devices and memory technologies. These patents describe various innovative structures and configurations aimed at improving the performance and efficiency of these devices.
 +
 +
Summary:
 +
- The patents cover semiconductor apparatus with multiple semiconductor unit devices, photoelectric conversion devices, variable resistance memory devices, semiconductor memory devices with unique memory cell structures, and specific components and their arrangement in semiconductor memory devices.
 +
- The patents also describe a semiconductor device with a unique channel pattern, a semiconductor device consisting of two semiconductor structures, a semiconductor device with a lower structure and a stack structure, a vertical memory device, and a semiconductor device with isolation structures and gate structures.
 +
- Notable applications include the use of superlattice-like structures in phase change material layers, modification of energy levels in photoelectric conversion layers to enhance efficiency, and specific arrangements of components in semiconductor memory devices.
 +
- The patents also mention the use of these technologies in sensors, electronic devices, and memory devices.
 +
 +
Bullet points:
 +
* Samsung Electronics Co., Ltd. has filed patents for semiconductor apparatus, photoelectric conversion devices, variable resistance memory devices, and semiconductor memory devices.
 +
* The patents describe innovative structures and configurations to improve performance and efficiency.
 +
* Notable applications include superlattice-like structures in phase change material layers and modification of energy levels in photoelectric conversion layers.
 +
* The patents also mention the use of these technologies in sensors, electronic devices, and memory devices.
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==Patent applications for Samsung Electronics Co., Ltd. on November 2nd, 2023==
 
==Patent applications for Samsung Electronics Co., Ltd. on November 2nd, 2023==
  
Line 1,080: Line 1,099:
 
Insik LEE
 
Insik LEE
  
−
 
−
'''Brief explanation'''
 
−
The patent application describes an electronic device with a Bluetooth communication module, memory, and processor.
 
−
* The device can receive a request from another device to increase the transmission power during Bluetooth communication.
 
−
* It compares the requested power level with a second maximum power level, which is lower than the device's first maximum power level.
 
−
* If the requested power level is below the second maximum, the device increases its transmission power and sends a message to the other device indicating the power increase.
 
−
 
−
'''Abstract'''
 
−
An electronic device is provided. The electronic device includes a Bluetooth communication module, a memory, and a processor operatively connected to the Bluetooth communication circuit and the memory, wherein the processor may be configured to perform the operations of receiving, through the Bluetooth communication module, a transmission power increase request from an external electronic device during Bluetooth communication with the external electronic device, compare a transmission power level based on the received increase request with a second maximum transmission power level which is designated to be smaller than a first maximum transmission power level that can be provided by the electronic device, when the transmission power level based on the increase request is less than the second maximum transmission power level, transmit a message indicating an increase in the transmission power level to the external electronic device after the transmission power level of the Bluetooth communication circuit is increased.
 
  
 
===METHODS AND APPARATUS FOR ROUND-TRIP-TIME MEASUREMENT ON A SL INTERFACE ([[US Patent Application 18303350. METHODS AND APPARATUS FOR ROUND-TRIP-TIME MEASUREMENT ON A SL INTERFACE simplified abstract|18303350]])===
 
===METHODS AND APPARATUS FOR ROUND-TRIP-TIME MEASUREMENT ON A SL INTERFACE ([[US Patent Application 18303350. METHODS AND APPARATUS FOR ROUND-TRIP-TIME MEASUREMENT ON A SL INTERFACE simplified abstract|18303350]])===
Line 1,097: Line 1,107:
 
Emad N. Farag
 
Emad N. Farag
  
−
 
−
'''Brief explanation'''
 
−
The patent application describes a method for operating a user equipment (UE) in a wireless communication system.
 
−
 
−
* The method involves receiving a positioning reference signal (PRS) from another UE in a specific time slot.
 
−
* The UE measures the receive timing of the PRS in that time slot.
 
−
* The UE determines the reference transmit timing of the time slot.
 
−
* The UE calculates the time difference between the receive and transmit timings of the PRS.
 
−
* Based on this time difference, the UE determines information for a report.
 
−
 
−
This method allows the UE to accurately measure the timing difference between the receive and transmit signals, which can be used for various purposes in the wireless communication system.
 
−
 
−
'''Abstract'''
 
−
A method of operating a user equipment (UE) is provided. The method includes receiving, from a second UE, a first sidelink (SL) positioning reference signal (PRS) in slot m; measuring a receive (Rx) timing of the first SL PRS in the slot m; and determining a reference transmit (Tx) timing of the slot m. The method further includes determining a first SL Rx - Tx time difference as a difference between the Rx timing of the first SL PRS in the slot m and the reference Tx timing of the slot m and determine information for a first report based on the first SL Rx - Tx time difference.
 
  
 
===METHOD AND APPARATUS FOR RESOURCE ALLOCATION FOR SIDELINK POSITIONING IN A WIRELESS COMMUNICATION SYSTEM ([[US Patent Application 18138881. METHOD AND APPARATUS FOR RESOURCE ALLOCATION FOR SIDELINK POSITIONING IN A WIRELESS COMMUNICATION SYSTEM simplified abstract|18138881]])===
 
===METHOD AND APPARATUS FOR RESOURCE ALLOCATION FOR SIDELINK POSITIONING IN A WIRELESS COMMUNICATION SYSTEM ([[US Patent Application 18138881. METHOD AND APPARATUS FOR RESOURCE ALLOCATION FOR SIDELINK POSITIONING IN A WIRELESS COMMUNICATION SYSTEM simplified abstract|18138881]])===
Line 1,119: Line 1,115:
 
Miao ZHOU
 
Miao ZHOU
  
−
 
−
'''Brief explanation'''
 
−
- The patent application relates to methods and apparatuses in a 5G or 6G communication system.
 
−
- It focuses on determining resources for transmitting a sidelink positioning signal.
 
−
- The sidelink positioning signal is transmitted on the determined resources.
 
−
- The resources for transmitting the sidelink positioning signal can be determined based on mapping rules, specific parameters, or information indicated by received sidelink control information.
 
−
- Inter-node coordination information can also be used to determine the resources for transmitting the sidelink positioning signal.
 
−
- Request signaling can trigger the transmission of the sidelink positioning signal, and the resources can be determined based on information indicated in the request signaling.
 
−
- Channel sensing can also be used to determine the resources for transmitting the sidelink positioning signal.
 
−
 
−
'''Abstract'''
 
−
The disclosure relates to methods and apparatuses in a 5G or 6G communication system. Resources are determined for transmitting a sidelink positioning signal. The sidelink positioning signal is transmitted on the determined resources. Determining the resources for transmitting the sidelink positioning signal includes at least one of: determining the resources for transmitting the sidelink positioning signal based on at least one of a mapping rule and specific parameters; determining the resources for transmitting the sidelink positioning signal based on information indicated by received first sidelink control information sidelink control information (SCI); determining the resources for transmitting the sidelink positioning signal based on received inter-node coordination information; determining the resources for transmitting the sidelink positioning signal based on information indicated in request signaling if triggered by the request signaling to transmit the sidelink positioning signal; and determining the resources for transmitting the sidelink positioning signal based on channel sensing.
 
  
 
===LATENCY REDUCTION FOR TRANSMISSION OR RECEPTION OF DATA ([[US Patent Application 18299629. LATENCY REDUCTION FOR TRANSMISSION OR RECEPTION OF DATA simplified abstract|18299629]])===
 
===LATENCY REDUCTION FOR TRANSMISSION OR RECEPTION OF DATA ([[US Patent Application 18299629. LATENCY REDUCTION FOR TRANSMISSION OR RECEPTION OF DATA simplified abstract|18299629]])===
Line 1,139: Line 1,123:
 
Aris Papasakellariou
 
Aris Papasakellariou
  
−
 
−
'''Brief explanation'''
 
−
The patent application describes a method and apparatus for reducing latency in the transmission or reception of data.
 
−
 
−
* The method involves a user equipment (UE) receiving information for two different configured grant (CG) configurations.
 
−
* The first CG configuration enables scheduling by downlink control information (DCI) formats for physical uplink shared channels (PUSCHs) with transport blocks (TBs) associated with it.
 
−
* The second CG configuration disables scheduling by DCI formats for PUSCHs with TBs associated with it.
 
−
* A timer is started after the transmission of a PUSCH with a TB associated with the first CG configuration.
 
−
* The timer is ignored after the transmission of a PUSCH with a TB associated with the second CG configuration.
 
−
* The method also includes transmitting a first PUSCH with the first TB.
 
−
 
−
Overall, the patent application presents a method and apparatus for reducing latency in data transmission or reception by efficiently managing the scheduling of PUSCHs with different TB configurations.
 
−
 
−
'''Abstract'''
 
−
Apparatuses and methods for latency reduction for transmission or reception of data. A method performed by a user equipment (UE) includes receiving first information for a first configured grant (CG) configuration and second information for a second CG configuration. The method further includes determining: based on the first information, that scheduling by downlink control information (DCI) formats for physical uplink shared channels (PUSCHs) with transport blocks (TBs) associated with the first CG configuration is enabled; based on the second information, that scheduling by DCI formats for PUSCHs with TBs associated with the second CG configuration is disabled; to start a timer after a first CG-PUSCH transmission with a first TB associated with the first CG configuration; and to ignore the timer after a second CG-PUSCH transmission with a second TB associated with the second CG configuration. The method further includes transmitting a first PUSCH with the first TB.
 
  
 
===PDCCH FOR MULTI-CELL SCHEDULING ([[US Patent Application 18301848. PDCCH FOR MULTI-CELL SCHEDULING simplified abstract|18301848]])===
 
===PDCCH FOR MULTI-CELL SCHEDULING ([[US Patent Application 18301848. PDCCH FOR MULTI-CELL SCHEDULING simplified abstract|18301848]])===
Line 1,162: Line 1,131:
 
Ebrahim MolavianJazi
 
Ebrahim MolavianJazi
  
−
 
−
'''Brief explanation'''
 
−
This patent application describes a method and apparatus for monitoring the physical downlink control channel (PDCCH) for multi-cell scheduling.
 
−
 
−
* The method involves receiving information about sets of cells and a user equipment (UE)-specific search space (USS) set for PDCCH receptions on a scheduling cell.
 
−
* The USS set is associated with a downlink control information (DCI) format for scheduling on multiple cells.
 
−
* The method further includes determining a set of cells associated with the USS set and a reference cell from the set of cells.
 
−
* The size of the DCI format is counted in the number of sizes of DCI formats for scheduling on the reference cell, but not counted for cells other than the reference cell from the set of cells.
 
−
 
−
In summary, this patent application presents a method and apparatus for efficiently monitoring the PDCCH for multi-cell scheduling by counting the size of the DCI format only for the reference cell and not for other cells in the set.
 
−
 
−
'''Abstract'''
 
−
Apparatuses and methods for physical downlink control channel (PDCCH) monitoring for multi-cell scheduling. A method includes receiving information for a number of sets of cells and information for a user equipment (UE)-specific search space (USS) set for receptions of PDCCH candidates on a scheduling cell. The USS set has a USS set identity and is associated with a downlink control information (DCI) format for scheduling on more than one cell. The method further includes determining a set of cells, from the number of sets of cells, that is associated with the USS set and a reference cell from the set of cells. A size of the DCI format is counted in a number of sizes of DCI formats for scheduling on the reference cell and is not counted in a number of sizes of DCI formats for scheduling on cells, other than the reference cell, from the set of cells.
 
  
 
===METHOD AND APPARATUS FOR GRANT-FREE DATA TRANSMISSION IN WIRELESS COMMUNICATION SYSTEM ([[US Patent Application 18346519. METHOD AND APPARATUS FOR GRANT-FREE DATA TRANSMISSION IN WIRELESS COMMUNICATION SYSTEM simplified abstract|18346519]])===
 
===METHOD AND APPARATUS FOR GRANT-FREE DATA TRANSMISSION IN WIRELESS COMMUNICATION SYSTEM ([[US Patent Application 18346519. METHOD AND APPARATUS FOR GRANT-FREE DATA TRANSMISSION IN WIRELESS COMMUNICATION SYSTEM simplified abstract|18346519]])===
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Sungjin PARK
 
Sungjin PARK
  
−
 
−
'''Brief explanation'''
 
−
The abstract describes a communication scheme and system that combines IoT technology and a 5G communication system to support faster data transfer rates than a 4G system.
 
−
 
−
* The communication scheme includes intelligent services such as smart home, smart building, smart city, smart car, health care, digital education, retail business, and security and safety-related services.
 
−
* The method involves a terminal in a communication system receiving a semi-persistent scheduling (SPS) configuration from a base station.
 
−
* The terminal identifies physical downlink shared channels (PDSCH) corresponding to the SPS configuration.
 
−
* If the PDSCHs overlap in time in a slot, the terminal determines the PDSCH with the lowest SPS configuration index.
 
−
* The terminal then excludes the PDSCH with the lowest SPS configuration index and selects a PDSCH for data transmission.
 
−
* The terminal receives data from the base station based on the determined PDSCH, which is not overlapped with an uplink symbol in the slot.
 
−
 
−
'''Abstract'''
 
−
A communication scheme and a system of converging an IoT technology and a 5generation (5G) communication system for supporting a higher data transfer rate beyond a 4generation (4G) system are provided. The communication scheme includes intelligent services (e.g. smart home, smart building, smart city, smart car or connected car, health care, digital education, retail business, and security and safety-related services), based on a 5G communication technology and an IoT-related technology. A method performed by a terminal in a communication system is provided. The method includes receiving, from a base station, a semi-persistent scheduling (SPS) configuration including an SPS configuration index; identifying at least one physical downlink shared channel (PDSCH) corresponding to the SPS configuration; identifying a PDSCH with a lowest SPS configuration index in case that the at least one PDSCH corresponding to the SPS configuration is overlapped in time in a slot; determining a PDSCH for data transmission based on excluding a PDSCH that is overlapped with the PDSCH with the lowest SPS configuration index from the at least one PDSCH; and receiving, from the base station, data based on the determined PDSCH, wherein the at least one PDSCH is not overlapped with a symbol indicated as an uplink in the slot.
 
  
 
===TRANSMISSION METHOD AND APPARATUS FOR MIMO SYSTEM ([[US Patent Application 18349561. TRANSMISSION METHOD AND APPARATUS FOR MIMO SYSTEM simplified abstract|18349561]])===
 
===TRANSMISSION METHOD AND APPARATUS FOR MIMO SYSTEM ([[US Patent Application 18349561. TRANSMISSION METHOD AND APPARATUS FOR MIMO SYSTEM simplified abstract|18349561]])===
Line 1,204: Line 1,147:
 
Jonghwan KIM
 
Jonghwan KIM
  
−
 
−
'''Brief explanation'''
 
−
- This patent application describes a communication technique that combines IoT technology and a 5G communication system to support faster data transmission rates than the previous 4G system.
 
−
- The method involves using intelligence services such as smart homes, smart buildings, smart cities, smart cars, healthcare, digital education, retail businesses, security, and safety services, among others.
 
−
- The method determines scheduling-related parameters for users and transmits this information to a radio unit (RU).
 
−
- The scheduling information includes a first section extension field that contains information about the user equipment identifier (ueID) for each user.
 
−
- The scheduling information also includes a second section extension field that contains information about the number of ueIDs corresponding to each user.
 
−
 
−
'''Abstract'''
 
−
A communication technique for convergence between an IoT technology and a 5generation (5G) communication system for supporting a higher data transmission rate beyond a 4generation (4G) system, and a system thereof is provided. The method includes intelligence services (for example, smart homes, smart buildings, smart cities, smart cars or connected cars, healthcare, digital education, retail businesses, security and safety related services, and the like.) On the basis of a 5G communication technology and an IoT-related technology. A method includes determining a scheduling-related parameter for at least one user, and transmitting scheduling information indicating the scheduling-related parameter to a radio unit (RU), wherein the scheduling information includes a first section extension field including information relating to a user equipment identifier (ueID) related to the at least one user, and a second section extension field including information relating to a number of ueIDs corresponding to each user.
 
  
 
===TRANSMISSION METHOD AND APPARATUS FOR MIMO SYSTEM ([[US Patent Application 18349585. TRANSMISSION METHOD AND APPARATUS FOR MIMO SYSTEM simplified abstract|18349585]])===
 
===TRANSMISSION METHOD AND APPARATUS FOR MIMO SYSTEM ([[US Patent Application 18349585. TRANSMISSION METHOD AND APPARATUS FOR MIMO SYSTEM simplified abstract|18349585]])===
Line 1,222: Line 1,155:
 
Jonghwan KIM
 
Jonghwan KIM
  
−
 
−
'''Brief explanation'''
 
−
- The patent application describes a communication technique that combines IoT technology and a 5G communication system.
 
−
- The purpose of this technique is to support a higher data transmission rate than the previous 4G system.
 
−
- The method involves using intelligence services such as smart homes, buildings, cities, cars, healthcare, education, retail, and security.
 
−
- The method determines scheduling-related parameters for users and transmits this information to a radio unit.
 
−
- The scheduling information includes user equipment identifiers (ueIDs) and the number of ueIDs corresponding to each user.
 
−
 
−
'''Abstract'''
 
−
A communication technique for convergence between an IoT technology and a 5generation (5G) communication system for supporting a higher data transmission rate beyond a 4generation (4G) system, and a system thereof is provided. The method includes intelligence services (for example, smart homes, smart buildings, smart cities, smart cars or connected cars, healthcare, digital education, retail businesses, security and safety related services, and the like.) On the basis of a 5G communication technology and an IoT-related technology. A method includes determining a scheduling-related parameter for at least one user, and transmitting scheduling information indicating the scheduling-related parameter to a radio unit (RU), wherein the scheduling information includes a first section extension field including information relating to a user equipment identifier (ueID) related to the at least one user, and a second section extension field including information relating to a number of ueIDs corresponding to each user.
 
  
 
===METHOD AND APPARATUS FOR HANDLING MSGA RETRANSMISSIONS DURING TWO STEP RANDOM ACCESS PROCEDURES IN WIRELESS COMMUNICATION SYSTEM ([[US Patent Application 18345195. METHOD AND APPARATUS FOR HANDLING MSGA RETRANSMISSIONS DURING TWO STEP RANDOM ACCESS PROCEDURES IN WIRELESS COMMUNICATION SYSTEM simplified abstract|18345195]])===
 
===METHOD AND APPARATUS FOR HANDLING MSGA RETRANSMISSIONS DURING TWO STEP RANDOM ACCESS PROCEDURES IN WIRELESS COMMUNICATION SYSTEM ([[US Patent Application 18345195. METHOD AND APPARATUS FOR HANDLING MSGA RETRANSMISSIONS DURING TWO STEP RANDOM ACCESS PROCEDURES IN WIRELESS COMMUNICATION SYSTEM simplified abstract|18345195]])===
Line 1,240: Line 1,163:
 
Anil AGIWAL
 
Anil AGIWAL
  
−
 
−
'''Brief explanation'''
 
−
- The patent application is about a communication method and system that combines 5G technology and IoT technology.
 
−
- It aims to support higher data rates beyond what a 4G system can provide.
 
−
- The technology can be used in various intelligent services such as smart homes, smart buildings, smart cities, smart cars, health care, digital education, smart retail, security, and safety services.
 
−
- The patent application specifically focuses on a method and apparatus for handling message A retransmission during 2 step random access procedures.
 
−
 
−
'''Abstract'''
 
−
The disclosure relates to a communication method and system for converging a 5th-Generation (5G) communication system for supporting higher data rates beyond a 4th-Generation (4G) system with a technology for the Internet of things (IoT). The present disclosure may be applied to intelligent services based on 5G communication technology and IoT-related technology, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. The present disclosure provides a method and apparatus for handling message A retransmission during 2 step random access procedures.
 
  
 
===SYSTEM AND METHOD OF SELECTING RACH OCCASIONS FOR SYSTEM INFORMATION REQUEST ([[US Patent Application 18346603. SYSTEM AND METHOD OF SELECTING RACH OCCASIONS FOR SYSTEM INFORMATION REQUEST simplified abstract|18346603]])===
 
===SYSTEM AND METHOD OF SELECTING RACH OCCASIONS FOR SYSTEM INFORMATION REQUEST ([[US Patent Application 18346603. SYSTEM AND METHOD OF SELECTING RACH OCCASIONS FOR SYSTEM INFORMATION REQUEST simplified abstract|18346603]])===
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Anil AGIWAL
 
Anil AGIWAL
  
−
 
−
'''Brief explanation'''
 
−
The abstract describes a method for a User Equipment (UE) in a wireless communication system to request system information from a base station. The method involves the following steps:
 
−
 
−
* The UE receives configuration information from the base station through higher layer signaling. This configuration information includes details about the period for requesting system information, which is divided into multiple association periods.
 
−
* The UE identifies the specific resources required for requesting the system information based on the received configuration information. These resources include an index of the association period within the request period, information about a random access preamble, and information about a Random Access Channel (RACH) occasion.
 
−
* Finally, the UE transmits the system information request to the base station using the identified resources.
 
−
 
−
In summary, the method provides a way for a UE to efficiently request system information from a base station in a wireless communication system.
 
−
 
−
'''Abstract'''
 
−
A method of a UE is provided. The method includes receiving, from a base station, configuration information for a system information (SI) request by higher layer signaling, the configuration information including information on a SI request period comprising of a number of association period; identifying information on a SI request resource corresponding to a SI message based on the configuration information, the information on the SI request resource including an index of an association period in the SI request period, information on a random access preamble, and information on a RACH occasion; and transmitting, to the base station, the SI request for the SI message based on the information on the SI request resource.
 
  
 
===METHOD AND APPARATUS FOR RECOVERY FROM FALLBACK FOR CELLULAR INTERNET OF THINGS DEVICE ([[US Patent Application 17796472. METHOD AND APPARATUS FOR RECOVERY FROM FALLBACK FOR CELLULAR INTERNET OF THINGS DEVICE simplified abstract|17796472]])===
 
===METHOD AND APPARATUS FOR RECOVERY FROM FALLBACK FOR CELLULAR INTERNET OF THINGS DEVICE ([[US Patent Application 17796472. METHOD AND APPARATUS FOR RECOVERY FROM FALLBACK FOR CELLULAR INTERNET OF THINGS DEVICE simplified abstract|17796472]])===
Line 1,277: Line 1,179:
 
Mahmoud WATFA
 
Mahmoud WATFA
  
−
 
−
'''Brief explanation'''
 
−
The patent application describes three methods for a User Equipment (UE) in 5GMM-CONNECTED mode with RRC inactive indication.
 
−
 
−
* Method 1:
 
−
- Establish a PDU session for sending data over the control plane.
 
−
- If there is data to be sent in an UL NAS TRANSPORT message, request lower layers to resume an RRC connection.
 
−
- Upon receiving a fallback indication from the lower layers, enter 5GMM-IDLE mode.
 
−
 
−
* Method 2:
 
−
- Establish a PDU session for sending data over the user plane.
 
−
- If there is user data to be sent over the user plane and no pending NAS procedure, enter 5GMM-IDLE mode upon receiving a fallback indication from the lower layers.
 
−
 
−
* Method 3:
 
−
- In response to receiving a suspend indication from the lower layer, determine the type of the suspend indication.
 
−
- Enter a NAS mode according to the determined type of the suspend indication.
 
−
 
−
'''Abstract'''
 
−
There is disclosed a first method for a UE, wherein the UE is in 5GMM-CONNECTED mode with RRC inactive indication. The first method comprises: establishing a PDU session for sending data over the control plane; determining that there is data to be sent in an UL NAS TRANSPORT message; in response to the determining, requesting lower layers to resume an RRC connection; and upon receiving a fallback indication from the lower layers in response to the requesting, entering 5GMM-IDLE mode. Also disclosed is a second method for a UE, wherein the UE is in 5GMM-CONNECTED mode with RRC inactive indication. The second method comprises: establishing a PDU session for sending data over the user plane; determining that there is user data to be sent over the user plane; determining that there is no pending NAS procedure; and upon receiving a fallback indication from the lower layers, in response to the determining, entering 5GMM-IDLE mode. Also disclosed is a third method for a UE, wherein the UE is in 5GMM-CONNECTED mode with RRC inactive indication. The third method comprises: in response to receiving, from lower layer, a suspend indication, determining the type of the suspend indication; and entering a NAS mode according to the determined type of the suspend indication.
 
  
 
===CIRCUIT BOARD AND ELECTRONIC DEVICE INCLUDING CIRCUIT BOARD ([[US Patent Application 17904220. CIRCUIT BOARD AND ELECTRONIC DEVICE INCLUDING CIRCUIT BOARD simplified abstract|17904220]])===
 
===CIRCUIT BOARD AND ELECTRONIC DEVICE INCLUDING CIRCUIT BOARD ([[US Patent Application 17904220. CIRCUIT BOARD AND ELECTRONIC DEVICE INCLUDING CIRCUIT BOARD simplified abstract|17904220]])===
Line 1,304: Line 1,187:
 
Bumhee BAE
 
Bumhee BAE
  
−
 
−
'''Brief explanation'''
 
−
The patent application describes an electronic device with a circuit board that connects two electric elements.
 
−
* The circuit board has three portions - a first portion, a second portion, and a third portion.
 
−
* The second and third portions extend from the first portion.
 
−
* The circuit board includes signal lines, ground patterns, and conductive vias.
 
−
* The signal lines connect the second and third portions.
 
−
* The ground patterns also connect the second and third portions.
 
−
* The first conductive vias connect the ground patterns at the second portion.
 
−
* The second conductive vias connect the ground patterns at the third portion.
 
−
* The ground patterns have a meander form at the first portion.
 
−
 
−
'''Abstract'''
 
−
An electronic device includes a first electric element a second electric element, and a circuit board. The circuit board is configured to deliver a signal between the first electric element and the second electric element. The circuit board includes a first portion, a second portion, and a third portion. The second and third portions extend from the first portion with the first portion therebetween. The circuit board also includes at least one signal line extending from the second portion to the third portion, a plurality of ground patterns extending from the second portion to the third portion, a plurality of first conductive vias positioned at the second portion and electrically connecting the plurality of ground patterns, and a plurality of second conductive vias positioned at the third portion and electrically connecting the plurality of ground patterns. The plurality of ground patterns include a meander form at the first portion.
 
  
 
===FLEXIBLE CIRCUIT BOARD AND ELECTRONIC DEVICE COMPRISING SAME ([[US Patent Application 18348622. FLEXIBLE CIRCUIT BOARD AND ELECTRONIC DEVICE COMPRISING SAME simplified abstract|18348622]])===
 
===FLEXIBLE CIRCUIT BOARD AND ELECTRONIC DEVICE COMPRISING SAME ([[US Patent Application 18348622. FLEXIBLE CIRCUIT BOARD AND ELECTRONIC DEVICE COMPRISING SAME simplified abstract|18348622]])===
Line 1,326: Line 1,195:
 
Youngsun LEE
 
Youngsun LEE
  
−
 
−
'''Brief explanation'''
 
−
The patent application describes an electronic device with a flexible circuit board connected to a main circuit board inside a housing.
 
−
* The flexible circuit board has a flexible circuit part and a joining part connected to the main circuit board.
 
−
* The joining part includes a first layer with connection holes, a second layer with connection holes, and a reinforcement member between the layers.
 
−
* The reinforcement member overlaps with the end part of the flexible circuit part.
 
−
* The purpose of this design is to provide strength and stability to the flexible circuit board connection.
 
−
 
−
'''Abstract'''
 
−
An electronic device is provided. The electronic device includes a housing, a main circuit board arranged inside the housing, and at least one flexible circuit board electrically connected to the main circuit board, wherein the flexible circuit board includes a flexible circuit part, and a joining part arranged on one end of the flexible circuit part and connected to the main circuit board. A first joining part includes a first layer oriented a first direction and having at least one first connection hole, a second layer oriented in a second direction opposite to the first direction and has at least one second connection hole, and a reinforcement member which is arranged between the first and the second layer and is connected to the flexible circuit part while being arranged such that at least a portion thereof overlaps with the one end part of the flexible circuit part.
 
  
 
===ELECTRONIC DEVICE INCLUDING FLEXIBLE PRINTED CIRCUIT BOARD ([[US Patent Application 18346880. ELECTRONIC DEVICE INCLUDING FLEXIBLE PRINTED CIRCUIT BOARD simplified abstract|18346880]])===
 
===ELECTRONIC DEVICE INCLUDING FLEXIBLE PRINTED CIRCUIT BOARD ([[US Patent Application 18346880. ELECTRONIC DEVICE INCLUDING FLEXIBLE PRINTED CIRCUIT BOARD simplified abstract|18346880]])===
Line 1,344: Line 1,203:
 
Yongyoun KIM
 
Yongyoun KIM
  
−
 
−
'''Brief explanation'''
 
−
The patent application describes an electronic device with a folding hinge structure and two connected housings.
 
−
* The device includes a hinge housing and a first housing connected to the hinge structure.
 
−
* A second housing is connected to the first housing through the hinge structure and can rotate with respect to the first housing.
 
−
* A flexible printed circuit board (FPCB) is used to connect the first and second housings.
 
−
* The FPCB has one end connected to a first printed circuit board (PCB) in the first housing and the other end connected to a second PCB in the second housing.
 
−
* The FPCB consists of a first section and a second section, with the second section extending from one side of the first section.
 
−
* The curvature of the second section varies more than the curvature of the first section when the first and second housings rotate with respect to the hinge structure.
 
−
 
−
'''Abstract'''
 
−
An electronic device includes: a hinge structure which is a folding area and includes a hinge housing; a first housing connected to the hinge structure; a second housing connected with the first housing through the hinge structure to be rotatable with respect to the first housing; and a flexible printed circuit board (FPCB), which has one end connected to a first printed circuit board (PCB) disposed in the first housing, and the other end connected to a second PCB disposed in the second housing. The FPCB includes a first section and a second section, the second section is extended from one side of the first section, and a variance in a curvature of the second section is greater than a variance in a curvature of the first section when the first housing and the second housing rotate with respect to the hinge structure.
 
  
 
===COVER PLATE FOR ELECTRONIC DEVICE AND ELECTRONIC DEVICE COMPRISING SAME ([[US Patent Application 18348661. COVER PLATE FOR ELECTRONIC DEVICE AND ELECTRONIC DEVICE COMPRISING SAME simplified abstract|18348661]])===
 
===COVER PLATE FOR ELECTRONIC DEVICE AND ELECTRONIC DEVICE COMPRISING SAME ([[US Patent Application 18348661. COVER PLATE FOR ELECTRONIC DEVICE AND ELECTRONIC DEVICE COMPRISING SAME simplified abstract|18348661]])===
Line 1,364: Line 1,211:
 
Hwanju JEON
 
Hwanju JEON
  
−
 
−
'''Brief explanation'''
 
−
The abstract describes a cover plate for an electronic device that has two layers and provides RF shielding effectiveness.
 
−
 
−
* The cover plate has a first layer with a first surface facing one direction and a second surface facing the opposite direction.
 
−
* A specified type of fiber is placed between the first and second surfaces of the first layer.
 
−
* The second layer, which is placed in the opposite direction of the first layer, provides a specified level of RF shielding effectiveness.
 
−
* The cover plate is designed to protect the electronic device from electromagnetic interference.
 
−
* The patent application suggests that there may be other embodiments or variations of this cover plate design.
 
−
 
−
'''Abstract'''
 
−
A cover plate for an electronic device may include: a first layer including a first surface facing a first direction, a second surface facing a second direction opposite to the first direction, and a specified type of fiber disposed between the first and second surfaces; and a second layer having a specified RF shielding effectiveness and disposed in the second direction with respect to the first layer. Various other embodiments are also possible.
 
  
 
===INTEGRATED CIRCUIT DEVICES INCLUDING A POWER DISTRIBUTION NETWORK AND METHODS OF FORMING THE SAME ([[US Patent Application 17816809. INTEGRATED CIRCUIT DEVICES INCLUDING A POWER DISTRIBUTION NETWORK AND METHODS OF FORMING THE SAME simplified abstract|17816809]])===
 
===INTEGRATED CIRCUIT DEVICES INCLUDING A POWER DISTRIBUTION NETWORK AND METHODS OF FORMING THE SAME ([[US Patent Application 17816809. INTEGRATED CIRCUIT DEVICES INCLUDING A POWER DISTRIBUTION NETWORK AND METHODS OF FORMING THE SAME simplified abstract|17816809]])===
Line 1,384: Line 1,219:
 
Inchan Hwang
 
Inchan Hwang
  
−
 
−
'''Brief explanation'''
 
−
The patent application describes integrated circuit devices and methods for their formation, specifically focusing on a static random access memory (SRAM) unit.
 
−
 
−
* The SRAM unit includes a first inverter on a substrate and a power distribution network (PDN) structure with a first power rail and a second power rail.
 
−
* The substrate extends between the first inverter and the PDN structure.
 
−
* The first inverter consists of a first upper transistor with a first upper source/drain region, a first lower transistor between the substrate and the first upper transistor with a first lower source/drain region.
 
−
* There is a first power contact that extends through the substrate and connects the first upper source/drain region to the first power rail.
 
−
* Additionally, there is a second power contact that extends through the substrate and connects the first lower source/drain region to the second power rail.
 
−
 
−
'''Abstract'''
 
−
Integrated circuit devices and methods of forming the same are provided. The integrated circuit devices may include a static random access memory (SRAM) unit. The SRAM unit may include a first inverter on a substrate and a power distribution network (PDN) structure including a first power rail and a second power rail. The substrate may extend between the first inverter and the PDN structure. The first inverter may include a first upper transistor including a first upper source/drain region, a first lower transistor between the substrate and the first upper transistor and including a first lower source/drain region, a first power contact extending through the substrate and electrically connecting the first upper source/drain region to the first power rail, and a second power contact extending through the substrate and electrically connecting the first lower source/drain region to the second power rail.
 
  
 
===SEMICONDUCTOR DEVICES ([[US Patent Application 18115116. SEMICONDUCTOR DEVICES simplified abstract|18115116]])===
 
===SEMICONDUCTOR DEVICES ([[US Patent Application 18115116. SEMICONDUCTOR DEVICES simplified abstract|18115116]])===
Line 1,404: Line 1,227:
 
Minjun Lee
 
Minjun Lee
  
−
 
−
'''Brief explanation'''
 
−
The patent application describes a semiconductor device with a gate electrode, a memory body structure, a source layer, and a drain layer.
 
−
* The gate electrode is located on a substrate.
 
−
* The memory body structure extends through the gate electrode.
 
−
* The source layer, located at one end of the memory body structure, is made of germanium doped with p-type impurities.
 
−
* The drain layer, located at the other end of the memory body structure, is made of a metal or metal alloy.
 
−
* The memory body structure consists of undoped polysilicon.
 
−
* The memory body structure also includes a charge storage pattern on the sidewall of the body.
 
−
* A blocking pattern is present on the outer sidewall of the charge storage pattern and makes contact with the gate electrode.
 
−
 
−
'''Abstract'''
 
−
A semiconductor device includes a gate electrode on a substrate, a memory body structure extending through the gate electrode, a source layer at an end portion of the memory body structure and including germanium doped with p-type impurities, and a drain layer at another end portion of the memory body structure and including a metal or a metal alloy. The memory body structure may include a body including undoped polysilicon, a charge storage pattern on a sidewall of the body, and a blocking pattern on an outer sidewall of the charge storage pattern and contacting the gate electrode.
 
  
 
===SEMICONDUCTOR DEVICE ([[US Patent Application 18062825. SEMICONDUCTOR DEVICE simplified abstract|18062825]])===
 
===SEMICONDUCTOR DEVICE ([[US Patent Application 18062825. SEMICONDUCTOR DEVICE simplified abstract|18062825]])===
Line 1,425: Line 1,235:
 
Kiseok Lee
 
Kiseok Lee
  
−
 
−
'''Brief explanation'''
 
−
The patent application describes a semiconductor device with a specific structure and arrangement of components.
 
−
 
−
* The device includes a bit line, which is a conductive line that extends in a certain direction.
 
−
* On top of the bit line, there is a semiconductor pattern that consists of two vertical portions and a horizontal portion.
 
−
* The two vertical portions are opposite to each other in the direction of the bit line.
 
−
* The horizontal portion connects the two vertical portions.
 
−
* Adjacent to the horizontal portion, there are two word lines, which are also conductive lines.
 
−
* A gate insulating pattern is present between each vertical portion and its corresponding word line.
 
−
* The bottom surface of the horizontal portion is positioned at a height that is either lower or equal to the uppermost surface of the bit line.
 
−
 
−
'''Abstract'''
 
−
A semiconductor device may include a bit line extending in a first direction, a semiconductor pattern on the bit line, the semiconductor pattern including first and second vertical portions, which are opposite to each other in the first direction, and a horizontal portion connecting the first and second vertical portions, first and second word lines on the horizontal portion to be adjacent to the first and second vertical portions, respectively, and a gate insulating pattern between the first vertical portion and the first word line and between the second vertical portion and the second word line. A bottom surface of the horizontal portion may be located at a height that is lower than or equal to the uppermost surface of the bit line.
 
  
 
===SEMICONDUCTOR DEVICE ([[US Patent Application 18304930. SEMICONDUCTOR DEVICE simplified abstract|18304930]])===
 
===SEMICONDUCTOR DEVICE ([[US Patent Application 18304930. SEMICONDUCTOR DEVICE simplified abstract|18304930]])===
Line 1,447: Line 1,243:
 
Yoongoo Kang
 
Yoongoo Kang
  
−
 
−
'''Brief explanation'''
 
−
The patent application describes a semiconductor device with various components and structures.
 
−
* The device includes an active region, an isolation region, and a gate trench.
 
−
* A gate structure is present in the gate trench.
 
−
* There are two impurity regions on both sides of the gate structure.
 
−
* A bit line structure is included, consisting of a line portion and a plug portion.
 
−
* The plug portion is electrically connected to one of the impurity regions.
 
−
* An insulating structure is present on the side surface of the plug portion.
 
−
* The insulating structure includes a spacer, an insulating pattern, and an insulating liner.
 
−
* The spacer is made of a first material, the insulating pattern is made of a second material, and the insulating liner is made of a third material.
 
−
 
−
'''Abstract'''
 
−
A semiconductor device includes an active region; an isolation region on a side surface of the active region; a gate trench intersecting the active region and extending into the isolation region; a gate structure in the gate trench; a first impurity region and a second impurity region in the active region on both sides of the gate structure and spaced apart from each other; a bit line structure including a line portion intersecting the gate structure and a plug portion below the line portion and electrically connected to the first impurity region; and an insulating structure on a side surface of the plug portion. The insulating structure includes a spacer including a first material; an insulating pattern between the plug portion and the spacer and including a second material; and an insulating liner covering a side surface and a bottom surface of the insulating pattern and including a third material.
 
  
 
===SEMICONDUCTOR MEMORY DEVICE ([[US Patent Application 18117604. SEMICONDUCTOR MEMORY DEVICE simplified abstract|18117604]])===
 
===SEMICONDUCTOR MEMORY DEVICE ([[US Patent Application 18117604. SEMICONDUCTOR MEMORY DEVICE simplified abstract|18117604]])===
Line 1,469: Line 1,251:
 
Kiseok LEE
 
Kiseok LEE
  
−
 
−
'''Brief explanation'''
 
−
The patent application describes a semiconductor memory device.
 
−
* The device includes a semiconductor substrate with an active portion defined by a device isolation layer.
 
−
* A bit line structure intersects the active portion on the substrate.
 
−
* A first conductive pad is located between the bit line structure and the active portion.
 
−
* A bit line contact pattern is positioned between the first conductive pad and the bit line structure.
 
−
* A first bit line contact spacer covers one side of the first conductive pad, while a second bit line contact spacer covers the other side.
 
−
* The first conductive pad has a flat bottom surface that contacts the top surface of the active portion.
 
−
* The width of the first bit line contact spacer is different from the width of the second bit line contact spacer.
 
−
 
−
'''Abstract'''
 
−
A semiconductor memory device includes a semiconductor substrate; a device isolation layer defining an active portion in the semiconductor substrate; a bit line structure intersecting the active portion on the semiconductor substrate; a first conductive pad between the bit line structure and the active portion; a bit line contact pattern between the first conductive pad and the bit line structure; a first bit line contact spacer covering a first sidewall of the first conductive pad; and a second bit line contact spacer covering a second sidewall of the first conductive pad, wherein the first conductive pad has a flat bottom surface that is in contact with a top surface of the active portion, and a width of the first bit line contact spacer is different from a width of the second bit line contact spacer.
 
  
 
===SEMICONDUCTOR DEVICES ([[US Patent Application 18220323. SEMICONDUCTOR DEVICES simplified abstract|18220323]])===
 
===SEMICONDUCTOR DEVICES ([[US Patent Application 18220323. SEMICONDUCTOR DEVICES simplified abstract|18220323]])===
Line 1,490: Line 1,259:
 
Dongoh KIM
 
Dongoh KIM
  
−
 
−
'''Brief explanation'''
 
−
The patent application describes a semiconductor device that includes two trenches in a substrate, with isolation structures and gate structures stacked in each trench.
 
−
 
−
* The device has first and second trenches in a substrate, with isolation structures and gate structures stacked in each trench.
 
−
* The first trench has a first inner wall oxide pattern, a first liner, and a first filling insulation pattern stacked in sequence.
 
−
* The second trench has a second inner wall oxide pattern, a second liner, and a second filling insulation pattern stacked in sequence.
 
−
* The first and second gate structures are stacked on the first and second regions, respectively.
 
−
* The first gate structure includes a first high-k dielectric pattern, a first P-type metal pattern, and a first N-type metal pattern.
 
−
* The second gate structure includes a second high-k dielectric pattern and a second N-type metal pattern.
 
−
* The first and second liners protrude above the upper surfaces of the inner wall oxide patterns and filling insulation patterns.
 
−
 
−
'''Abstract'''
 
−
A semiconductor device includes first and second trenches in respective first and second regions in a substrate, a first isolation structure having a first inner wall oxide pattern, a first liner, and a first filling insulation pattern sequentially stacked I the first trench, a second isolation structure having a second inner wall oxide pattern, a second liner, and a second filling insulation pattern sequentially stacked I the second trench, a first gate structure having a first high-k dielectric pattern, a first P-type metal pattern, and a first N-type metal pattern sequentially stacked on the first region, and a second gate structure having a second high-k dielectric pattern and a second N-type metal pattern sequentially stacked on the second region, wherein the first and second liners protrude above upper surfaces of the first and second inner wall oxide patterns and the first and second filling insulation patterns, respectively.
 
  
 
===SEMICONDUCTOR DEVICES ([[US Patent Application 18220327. SEMICONDUCTOR DEVICES simplified abstract|18220327]])===
 
===SEMICONDUCTOR DEVICES ([[US Patent Application 18220327. SEMICONDUCTOR DEVICES simplified abstract|18220327]])===
Line 1,512: Line 1,267:
 
Dongoh KIM
 
Dongoh KIM
  
−
 
−
'''Brief explanation'''
 
−
The patent application describes a semiconductor device with two trenches in different regions of a substrate.
 
−
* The device includes isolation structures made up of oxide patterns, liners, and insulation patterns stacked in the trenches.
 
−
* There are also gate structures made up of high-k dielectric patterns and metal patterns stacked on the regions.
 
−
* The liners protrude above the oxide patterns and insulation patterns in the trenches.
 
−
 
−
'''Abstract'''
 
−
A semiconductor device includes first and second trenches in respective first and second regions in a substrate, a first isolation structure having a first inner wall oxide pattern, a first liner, and a first filling insulation pattern sequentially stacked I the first trench, a second isolation structure having a second inner wall oxide pattern, a second liner, and a second filling insulation pattern sequentially stacked I the second trench, a first gate structure having a first high-k dielectric pattern, a first P-type metal pattern, and a first N-type metal pattern sequentially stacked on the first region, and a second gate structure having a second high-k dielectric pattern and a second N-type metal pattern sequentially stacked on the second region, wherein the first and second liners protrude above upper surfaces of the first and second inner wall oxide patterns and the first and second filling insulation patterns, respectively.
 
  
 
===VERTICAL MEMORY DEVICES ([[US Patent Application 18220073. VERTICAL MEMORY DEVICES simplified abstract|18220073]])===
 
===VERTICAL MEMORY DEVICES ([[US Patent Application 18220073. VERTICAL MEMORY DEVICES simplified abstract|18220073]])===
Line 1,529: Line 1,275:
 
DONGHWAN KIM
 
DONGHWAN KIM
  
−
 
−
'''Brief explanation'''
 
−
The patent application describes a vertical memory device with gate electrodes, a channel, a conductive through via, and insulation structures.
 
−
* The gate electrodes are arranged in a staircase shape on a substrate.
 
−
* The channel runs through the gate electrodes.
 
−
* A conductive through via connects to a first gate electrode and extends through the second gate electrodes below it.
 
−
* Insulation structures separate the conductive through via from the sidewalls of the second gate electrodes.
 
−
 
−
'''Abstract'''
 
−
A vertical memory device includes gate electrodes, a channel, a first conductive through via, and insulation structures. The gate electrodes are spaced apart from each other on a substrate in a first direction substantially perpendicular to an upper surface of the substrate, and may be stacked in a staircase shape. The channel extends through the gate electrodes in the first direction. The first conductive through via extends through a conductive pad of a first gate electrode among the gate electrodes and is electrically connected thereto. The first conductive through via extends through second gate electrodes from among the gate electrodes that are under the first gate electrode. The insulation structures are formed between the first conductive through via and sidewalls of each of the second gate electrodes, and electrically insulates the first conductive through via from each of the second gate electrodes.
 
  
 
===SEMICONDUCTOR DEVICES INCLUDING STACK STRUCTURE HAVING GATE REGION AND INSULATING REGION ([[US Patent Application 18348521. SEMICONDUCTOR DEVICES INCLUDING STACK STRUCTURE HAVING GATE REGION AND INSULATING REGION simplified abstract|18348521]])===
 
===SEMICONDUCTOR DEVICES INCLUDING STACK STRUCTURE HAVING GATE REGION AND INSULATING REGION ([[US Patent Application 18348521. SEMICONDUCTOR DEVICES INCLUDING STACK STRUCTURE HAVING GATE REGION AND INSULATING REGION simplified abstract|18348521]])===
Line 1,547: Line 1,283:
 
Geunwon LIM
 
Geunwon LIM
  
−
 
−
'''Brief explanation'''
 
−
The patent application describes a semiconductor device with a lower structure and a stack structure that extends into a connection region on the lower structure.
 
−
* The stack structure includes gate pads and mold pads.
 
−
* The mold pads consist of intermediate mold pads, including first intermediate mold pads and a second intermediate mold pad positioned between a pair of the first intermediate mold pads.
 
−
* Each first intermediate mold pad has a certain length in a specific direction, while the second intermediate mold pad has a greater length in the same direction.
 
−
* One of the intermediate mold pads has a mold pad portion and an insulating protrusion portion on the mold pad portion.
 
−
* Specifically, one of the first intermediate mold pads includes both the mold pad portion and the insulating protrusion portion.
 
−
* The central region of the second intermediate mold pad does not have the insulating protrusion portion.
 
−
 
−
'''Abstract'''
 
−
A semiconductor device includes a lower structure and a stack structure that extends into a connection region on the lower structure, where the stack structure includes gate pads and mold pads. The mold pads include intermediate mold pads that include first intermediate mold pads and a second intermediate mold pad between a pair of the first intermediate mold pads, each of the first intermediate mold pads has a first length in a first direction, the second intermediate mold pad has a second length in the first direction, greater than the first length, one of the intermediate mold pads includes a mold pad portion and an insulating protrusion portion on the mold pad portion, one of the first intermediate mold pads includes the mold pad portion and the insulating protrusion portion, and a central region of the second intermediate mold pad does not include the insulating protrusion portion.
 
  
 
===SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME ([[US Patent Application 18072312. SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME simplified abstract|18072312]])===
 
===SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME ([[US Patent Application 18072312. SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME simplified abstract|18072312]])===
Line 1,567: Line 1,291:
 
SEUNGMIN LEE
 
SEUNGMIN LEE
  
−
 
−
'''Brief explanation'''
 
−
The patent application describes a semiconductor device that consists of two semiconductor structures.
 
−
* The first semiconductor structure includes a substrate, circuit devices, and metal bonding layers.
 
−
* The second semiconductor structure includes gate electrodes, channel structures, metal bonding layers, bit lines, and source lines.
 
−
* The gate electrodes are stacked in a perpendicular direction to the metal bonding layers.
 
−
* The channel structures pass through the gate electrodes and extend in the same perpendicular direction.
 
−
* The metal bonding layers connect the first and second semiconductor structures.
 
−
* The bit lines are positioned below the channel structures and extend in a direction perpendicular to the gate electrodes.
 
−
* The source lines are placed on top of the channel structures and extend in a direction perpendicular to the bit lines.
 
−
* The channel structures are located at the intersections of the bit lines and source lines.
 
−
 
−
'''Abstract'''
 
−
A semiconductor device includes a first semiconductor structure including a first substrate, circuit devices disposed on the first substrate, and first metal bonding layers disposed on the circuit devices, and a second semiconductor structure including gate electrodes spaced apart from each other and stacked in a first direction, perpendicular to upper surfaces of the first metal bonding layers, channel structures passing through the gate electrodes, extending in the first direction, and respectively including a channel layer, second metal bonding layers disposed below the channel structures and the gate electrodes and connected to the first metal bonding layers, bit lines disposed below the channel structures, extending in a second direction, perpendicular to the first direction, and spaced apart from each other, and source lines disposed on the channel structures, extending in a third direction, perpendicular to the second direction, and spaced apart from each other. The channel structures are respectively disposed in intersection regions in which the bit lines and the source lines intersect each other.
 
  
 
===SEMICONDUCTOR MEMORY DEVICE ([[US Patent Application 18175198. SEMICONDUCTOR MEMORY DEVICE simplified abstract|18175198]])===
 
===SEMICONDUCTOR MEMORY DEVICE ([[US Patent Application 18175198. SEMICONDUCTOR MEMORY DEVICE simplified abstract|18175198]])===
Line 1,589: Line 1,299:
 
Teawon KIM
 
Teawon KIM
  
−
 
−
'''Brief explanation'''
 
−
The patent application describes a semiconductor memory device that includes a bit line, a channel pattern, a word line, and a gate insulating pattern.
 
−
* The channel pattern consists of a horizontal channel portion on the bit line and a vertical channel portion that extends vertically from the horizontal channel portion.
 
−
* The word line is located on the horizontal channel portion and on the sidewall of the vertical channel portion.
 
−
* A gate insulating pattern is positioned between the word line and the channel pattern.
 
−
* The channel pattern is made of an oxide semiconductor and is composed of three sequentially stacked layers: first, second, and third channel layers.
 
−
* The first to third channel layers contain a first metal, while the second channel layer also includes a second metal that is different from the first metal.
 
−
* At least a portion of the first channel layer makes contact with the bit line.
 
−
 
−
'''Abstract'''
 
−
A semiconductor memory device includes a bit line, a channel pattern including a horizontal channel portion on the bit line and a vertical channel portion vertically protruding from the horizontal channel portion, a word line on the horizontal channel portion and on a sidewall of the vertical channel portion, and a gate insulating pattern between the word line and the channel pattern. The channel pattern includes an oxide semiconductor and includes first, second, and third channel layers sequentially stacked. The first to third channel layers include a first metal, and the second channel layer further includes a second metal different from the first metal. At least a portion of the first channel layer contacts the bit line.
 
  
 
===SEMICONDUCTOR MEMORY DEVICE ([[US Patent Application 18104882. SEMICONDUCTOR MEMORY DEVICE simplified abstract|18104882]])===
 
===SEMICONDUCTOR MEMORY DEVICE ([[US Patent Application 18104882. SEMICONDUCTOR MEMORY DEVICE simplified abstract|18104882]])===
Line 1,609: Line 1,307:
 
Yong Jae LEE
 
Yong Jae LEE
  
−
 
−
'''Brief explanation'''
 
−
The patent application describes a semiconductor memory device with specific components and their arrangement.
 
−
* The device includes a substrate, first and second electrodes, an OTS film, and an electrode spacer film.
 
−
* The OTS film is positioned between the first and second electrodes and has three surfaces: one in contact with the first electrode, one in contact with the second electrode, and one in contact with the electrode spacer film.
 
−
* The logical state of data stored in the OTS film is determined by the polarity of a program voltage.
 
−
* The innovation lies in the specific arrangement and configuration of the components in the semiconductor memory device.
 
−
 
−
'''Abstract'''
 
−
A semiconductor memory device includes a substrate, a first electrode on the substrate, a second electrode on the first electrode, an OTS film between the first electrode and the second electrode, and an electrode spacer film disposed on a part of a side wall of the OTS film, wherein the OTS film includes a first surface that is in contact with the first electrode, a second surface that is in contact with the second electrode, and a third surface that is in contact with the electrode spacer film, and a logical state of data stored in the OTS film is based on polarity of a program voltage.
 
  
 
===SEMICONDUCTOR MEMORY DEVICE ([[US Patent Application 18113717. SEMICONDUCTOR MEMORY DEVICE simplified abstract|18113717]])===
 
===SEMICONDUCTOR MEMORY DEVICE ([[US Patent Application 18113717. SEMICONDUCTOR MEMORY DEVICE simplified abstract|18113717]])===
Line 1,627: Line 1,315:
 
Jong Hyun PAEK
 
Jong Hyun PAEK
  
−
 
−
'''Brief explanation'''
 
−
The patent application describes a semiconductor memory device with a unique memory cell structure.
 
−
 
−
* The device includes a substrate, a first conductive line, and a second conductive line.
 
−
* The memory cell is located between the first and second conductive lines.
 
−
* The memory cell consists of a first electrode, a second electrode, and an OTS (Oxide Thin Film) layer.
 
−
* A high-concentration electrode is also present between the second electrode and the OTS film.
 
−
* The concentration of nitrogen in the second electrode is lower than in the high-concentration electrode.
 
−
* The logic state of the data stored in the OTS film is determined by the polarity of the program voltage.
 
−
 
−
'''Abstract'''
 
−
A semiconductor memory device includes a substrate, a first conductive line disposed on the substrate and extending in a first direction, a second conductive line disposed on the first conductive line, and extending in a second direction intersecting the first direction, and a memory cell disposed between the first conductive line and the second conductive line, wherein the memory cell includes, a first electrode connected to the first conductive line, a second electrode connected to the second conductive line, an OTS film disposed between the first electrode and the second electrode, a high-concentration electrode disposed between the second electrode and the OTS film, wherein a concentration of nitrogen contained in the second electrode is lower than a concentration of nitrogen contained in the high-concentration electrode, wherein a logic state of data stored in the OTS film is based on a polarity of a program voltage.
 
  
 
===VARIABLE RESISTANCE MEMORY DEVICE ([[US Patent Application 18104890. VARIABLE RESISTANCE MEMORY DEVICE simplified abstract|18104890]])===
 
===VARIABLE RESISTANCE MEMORY DEVICE ([[US Patent Application 18104890. VARIABLE RESISTANCE MEMORY DEVICE simplified abstract|18104890]])===
Line 1,648: Line 1,323:
 
Sung-Ho EUN
 
Sung-Ho EUN
  
−
 
−
'''Brief explanation'''
 
−
The patent application describes a variable resistance memory device.
 
−
* The device includes a substrate, a cell array region, a wiring region, an upper wiring structure, and a protective film.
 
−
* The cell array region contains multiple memory cells.
 
−
* The wiring region has an inter-wiring insulating film stacked on the cell array region.
 
−
* The upper wiring structure is located in the inter-wiring insulating film.
 
−
* The protective film covers the upper surface of the cell array region.
 
−
* Each memory cell consists of a switching pattern and a variable resistance pattern.
 
−
* The cell array region has first conductive lines extending in one direction and second conductive lines extending in a different direction.
 
−
* The memory cells are located at the intersections of the first and second conductive lines.
 
−
 
−
'''Abstract'''
 
−
A variable resistance memory device includes a substrate, a cell array region including a plurality of memory cells on the substrate, a wiring region which includes an inter-wiring insulating film stacked on the cell array region, and an upper wiring structure in the inter-wiring insulating film and a protective film which covers an upper surface of the cell array region, between the cell array region and the wiring region, wherein each of the memory cells includes a switching pattern and a variable resistance pattern, the cell array region further includes first conductive lines extending in a first direction, and a second conductive lines extending in a second direction intersecting the first direction, and the plurality of memory cells are disposed at an intersections of the first conductive lines and the second conductive lines.
 
  
 
===PHOTOELECTRIC CONVERSION DEVICE AND SENSOR AND ELECTRONIC DEVICE ([[US Patent Application 18347960. PHOTOELECTRIC CONVERSION DEVICE AND SENSOR AND ELECTRONIC DEVICE simplified abstract|18347960]])===
 
===PHOTOELECTRIC CONVERSION DEVICE AND SENSOR AND ELECTRONIC DEVICE ([[US Patent Application 18347960. PHOTOELECTRIC CONVERSION DEVICE AND SENSOR AND ELECTRONIC DEVICE simplified abstract|18347960]])===
Line 1,670: Line 1,331:
 
Daiki MINAMI
 
Daiki MINAMI
  
−
 
−
'''Brief explanation'''
 
−
- The patent application describes a photoelectric conversion device, which is a device that converts light into electrical energy.
 
−
- The device includes a first electrode, a second electrode, and a photoelectric conversion layer positioned between them.
 
−
- The photoelectric conversion layer consists of a first material, a second material, and a third material.
 
−
- The first and second materials form a pn junction, which is a type of semiconductor junction that allows current to flow in only one direction.
 
−
- The third material is different from the first and second materials and is used to modify the distribution of energy levels in the first or second material.
 
−
- The purpose of modifying the energy levels is to enhance the efficiency of the photoelectric conversion process.
 
−
- The patent application also mentions that the photoelectric conversion device can be used in sensors and electronic devices.
 
−
 
−
'''Abstract'''
 
−
Disclosed are a photoelectric conversion device, and a sensor and an electronic device including the same. The photoelectric conversion device may include a first electrode and a second electrode and a photoelectric conversion layer between the first electrode and the second electrode. The photoelectric conversion layer includes a first material and a second material, which form a pn junction, and a third material that is different from the first material and the second material. The third material is configured to modify a distribution of energy levels of the first material or the second material.
 
  
 
===SEMICONDUCTOR APPARATUS ([[US Patent Application 18349433. SEMICONDUCTOR APPARATUS simplified abstract|18349433]])===
 
===SEMICONDUCTOR APPARATUS ([[US Patent Application 18349433. SEMICONDUCTOR APPARATUS simplified abstract|18349433]])===
Line 1,689: Line 1,338:
  
 
Kiyeon YANG
 
Kiyeon YANG
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'''Brief explanation'''
 
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The patent application describes a semiconductor apparatus with multiple semiconductor unit devices.
 
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* Each semiconductor unit device is positioned between two insulating layers that are separated in a direction perpendicular to the substrate.
 
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* The semiconductor unit devices consist of a selection device layer and a phase change material layer that run parallel to the substrate.
 
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* The phase change material layer has a superlattice-like structure.
 
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* The phase change material layer is located along a recess portion created by the first insulating layer, second insulating layer, and selection device layer.
 
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'''Abstract'''
 
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A semiconductor apparatus may include a plurality of semiconductor unit devices. Each of the semiconductor unit devices may be arranged between a first insulating layer and a second insulating layer that are apart from each other in a direction normal to a substrate. Each of the semiconductor unit devices may include a selection device layer and a phase change material layer that extend side by side in a direction parallel to the substrate. The phase change material layer may have a superlattice-like structure. The phase change material layer may be arranged along a recess portion that is formed by the first insulating layer, the second insulating layer, and the selection device layer.
 

Latest revision as of 03:02, 4 December 2023

Summary of the patent applications from Samsung Electronics Co., Ltd. on November 2nd, 2023

Samsung Electronics Co., Ltd. has recently filed several patents related to semiconductor devices and memory technologies. These patents describe various innovative structures and configurations aimed at improving the performance and efficiency of these devices.

Summary: - The patents cover semiconductor apparatus with multiple semiconductor unit devices, photoelectric conversion devices, variable resistance memory devices, semiconductor memory devices with unique memory cell structures, and specific components and their arrangement in semiconductor memory devices. - The patents also describe a semiconductor device with a unique channel pattern, a semiconductor device consisting of two semiconductor structures, a semiconductor device with a lower structure and a stack structure, a vertical memory device, and a semiconductor device with isolation structures and gate structures. - Notable applications include the use of superlattice-like structures in phase change material layers, modification of energy levels in photoelectric conversion layers to enhance efficiency, and specific arrangements of components in semiconductor memory devices. - The patents also mention the use of these technologies in sensors, electronic devices, and memory devices.

Bullet points:

  • Samsung Electronics Co., Ltd. has filed patents for semiconductor apparatus, photoelectric conversion devices, variable resistance memory devices, and semiconductor memory devices.
  • The patents describe innovative structures and configurations to improve performance and efficiency.
  • Notable applications include superlattice-like structures in phase change material layers and modification of energy levels in photoelectric conversion layers.
  • The patents also mention the use of these technologies in sensors, electronic devices, and memory devices.



Contents

Patent applications for Samsung Electronics Co., Ltd. on November 2nd, 2023

CLEANING DEVICE HAVING CLEANER AND DOCKING STATION (18340315)

Main Inventor

Ingyu CHOI


MEDICAL DEVICE APPARATUS, SYSTEM, AND METHOD (18219378)

Main Inventor

Hyungwoo LEE


METHOD AND DEVICE FOR PROVIDING FEEDBACK FOR SAFE WALKING (18347276)

Main Inventor

Juyeon YOU


POWER SUPPLY DEVICE AND POWER SUPPLY CONTROL METHOD OF POWER SUPPLY DEVICE (18347954)

Main Inventor

Jongdo PARK


RESIN COMPOSITION FOR STRAP OF WEARABLE ELECTRONIC DEVICE, AND METHOD FOR MANUFACTURING SAME (18220582)

Main Inventor

Jihyoung CHOI


METHODS OF FABRICATING SAMPLE WAFERS (18301347)

Main Inventor

Hyungsuk MOON


NANOCRYSTALLINE BORON NITRIDE FILM, IMAGE SENSOR INCLUDING THE SAME, FIELD EFFECT TRANSISTOR INCLUDING THE SAME, AND METHOD OF FABRICATING THE NANOCRYSTALLINE BORON NITRIDE FILM (18193058)

Main Inventor

Taejin CHOI


WASHING MACHINE AND CONTROL METHOD THEREFOR (18347103)

Main Inventor

Hooijoong KIM


DRYER APPARATUS AND CONTROLLING METHOD THEREOF (18218765)

Main Inventor

Changwan KIM


AIR CONDITIONER (18213051)

Main Inventor

Sungoug CHO


REFRIGERATOR AND CONTROLLING METHOD THEREOF (18220579)

Main Inventor

Dohyung KIM


SPECTRAL FILTER, IMAGE SENSOR INCLUDING THE SPECTRAL FILTER, AND ELECTRONIC DEVICE INCLUDING THE SPECTRAL FILTER (18120872)

Main Inventor

Hyochul KIM


METHOD AND APPARATUS FOR GNSS OPERATION IN NON-TERRESTRIAL NETWORKS (18301813)

Main Inventor

Carmela Cozzo


METHOD AND DEVICE FOR ACQUIRING GLOBAL NAVIGATION SATELLITE SYSTEM (GNSS) POSITIONING INFORMATION (18139622)

Main Inventor

Min WU


QUANTUM DOTS AND DEVICES INCLUDING THE SAME (18220364)

Main Inventor

Tae Gon KIM


DISPLAY APPARATUS AND LIGHT SOURCE DEVICE THEREOF (17311118)

Main Inventor

Sungyeol KIM


FLEXIBLE DISPLAY AND ELECTRONIC DEVICE INCLUDING SAME (18219793)

Main Inventor

Jaehyun BAE


ELECTRONIC DEVICE INCLUDING AIR VENT HOLE (18347899)

Main Inventor

Minsu JUNG


ELECTRONIC DEVICE HAVING THERMAL DIFFUSION STRUCTURE (18346394)

Main Inventor

Ohhyuck KWON


POWER SUPPLY CIRCUIT AND ELECTRONIC DEVICE COMPRISING SAME (18346462)

Main Inventor

Taewoong KIM


REMOTE CONTROLLER AND CONTROLLING METHOD THEREOF (17311096)

Main Inventor

Wonjae LEE


ELECTRONIC DEVICE AND METHOD FOR CONTROLLING ELECTRONIC DEVICE (18348757)

Main Inventor

Heetae KIM


ELECTRONIC DEVICE AND SCREEN CONTROL METHOD THEREOF (18218689)

Main Inventor

Youngrog KIM


ELECTRONIC DEVICE AND OPERATION METHOD THEREFOR (18338848)

Main Inventor

Minhyo JUNG


ELECTRONIC APPARATUS AND METHOD FOR PROCESSING INPUT FROM STYLUS PEN IN ELECTRONIC APPARATUS (18348109)

Main Inventor

Chunbae PARK


METHOD OF WRITING DATA IN NONVOLATILE MEMORY DEVICE AND NONVOLATILE MEMORY DEVICE PERFORMING THE SAME (18346627)

Main Inventor

Wonhee CHO


PROMPT AND GRADUAL MIGRATION SCHEMES (18219547)

Main Inventor

Changho CHOI


STORAGE DEVICE INCLUDING NONVOLATILE MEMORY DEVICE AND CONTROLLER, CONTROLLER AND OPERATING METHOD OF NONVOLATILE MEMORY DEVICE (18345124)

Main Inventor

Jesuk YEON


DISPLAY DEVICE AND OPERATING METHOD THEREFOR (18220620)

Main Inventor

Euijun KIM


ELECTRONIC DEVICE FOR MULTI-DISPLAY CONTROL (18097874)

Main Inventor

Hyunseok KIM


DISPLAY DEVICE AND CONTROL METHOD FOR SAME (18219466)

Main Inventor

Byungjeong JEON


ELECTRONIC DEVICE AND OPERATION METHOD OF ELECTRONIC DEVICE (18350384)

Main Inventor

Woonsang SON


MEMORY DEVICE INCLUDING ADDRESS TABLE AND OPERATING METHOD FOR MEMORY CONTROLLER (18140974)

Main Inventor

CHINAM KIM


STORAGE DEVICE, MEMORY DEVICE, AND SYSTEM INCLUDING STORAGE DEVICE AND MEMORY DEVICE (18132734)

Main Inventor

Kyunghan LEE


SFF-TA-100X BASED MULTI-MODE PROTOCOLS SOLID STATE DEVICES (18220522)

Main Inventor

Sompong Paul Olarig


ELECTRONIC DEVICE AND METHOD FOR CONTROLLING POWER SUPPLY OF ELECTRONIC DEVICE (18346540)

Main Inventor

Junghun HAN


ELECTRONIC DEVICE COMPRISING SENSOR MODULE (18218693)

Main Inventor

Seonho Han


ELECTRONIC APPARATUS AND METHOD FOR CONTROLLING THEREOF (18221190)

Main Inventor

Soyoon PARK


NEURAL PROCESSOR (18219904)

Main Inventor

Ilia Ovsiannikov


METHOD OF TRAINING BINARIZED NEURAL NETWORK WITH PARAMETERIZED WEIGHT CLIPPING AND MEMORY DEVICE USING THE SAME (18171433)

Main Inventor

Taehee Han


METHOD FOR KNOWLEDGE DISTILLATION AND MODEL GENERTATION (18218405)

Main Inventor

Mete OZAY


STANDARD DYNAMIC RANGE (SDR) TO HIGH DYNAMIC RANGE (HDR)INVERSE TONE MAPPING USING MACHINE LEARNING (18304651)

Main Inventor

Bowen Zhao


SYSTEM AND METHOD FOR ADAPTIVE DISCRETE COSINE TRANSFORM (DCT) NOISE FILTERING FOR DIGITAL IMAGES (17930335)

Main Inventor

Zeeshan Nadir


METHOD AND APPARATUS WITH OBJECT TRACKING (17987231)

Main Inventor

Dongwook LEE


METHOD AND APPARATUS FOR PERFORMING ANCHOR BASED RENDERING FOR AUGMENTED REALITY MEDIA OBJECTS (18023179)

Main Inventor

Eric YIP


METHOD AND ELECTRONIC DEVICE FOR DETERMINING OPTIMAL GLOBAL ATTENTION IN DEEP LEARNING MODEL (18315072)

Main Inventor

Eega Revanth RAJ


METHOD AND SYSTEM FOR DETECTING PRIVATE VIDEO (18327385)

Main Inventor

Sukumar MOHARANA


ELECTRONIC DEVICE AND METHOD CAPABLE OF REDUCING AFTERIMAGE OF DISPLAY (18351110)

Main Inventor

Jungbae BAE


ELECTRONIC DEVICE AND UTTERANCE PROCESSING METHOD THEREOF (18219060)

Main Inventor

Hoseon SHIN


ELECTRONIC DEVICE AND CONTROLLING METHOD THEREOF (18219130)

Main Inventor

Min-seok KIM


GLOBAL DATA LINE OF MULTI-ARRAY SYNCHRONOUS RANDOM ACCESS MEMORY (SRAM) (18076388)

Main Inventor

Hee Choul PARK


MEMORY DEVICE INCLUDING MULTI-BIT CELL AND OPERATING METHOD THEREOF (18124094)

Main Inventor

Duhwi Kim


MAGNETIC MEMORY USING SPIN CURRENT, OPERATING METHOD THEREOF, AND ELECTRONIC APPARATUS INCLUDING MAGNETIC MEMORY (17964373)

Main Inventor

Kwangseok KIM


LATCH-BASED STORAGE CIRCUITS HAVING EFFICIENT INTEGRATED CIRCUIT LAYOUTS (18157035)

Main Inventor

Kijun Lee


METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE (18183571)

Main Inventor

Yurim KIM


CHEMICAL MECHANICAL POLISHING METHOD AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE USING THE SAME (18190300)

Main Inventor

Yearin Byun


INTERPOSER AND SEMICONDUCTOR PACKAGE INCLUDING SAME (18347519)

Main Inventor

Ungcheon Kim


INTEGRATED CIRCUIT DEVICES INCLUDING A VIA AND METHODS OF FORMING THE SAME (17822246)

Main Inventor

JAEMYUNG CHOI


INTEGRATED CIRCUIT DEVICES INCLUDING VIA STRUCTURES HAVING A NARROW UPPER PORTION, AND RELATED FABRICATION METHODS (17880554)

Main Inventor

Tae Sun Kim


INTEGRATED CIRCUIT DEVICES INCLUDING METAL LINES SPACED APART FROM METAL VIAS, AND RELATED FABRICATION METHODS (17820949)

Main Inventor

Janggeun Lee


CONNECTION SCHEME WITH BACKSIDE POWER DISTRIBUTION NETWORK (17853867)

Main Inventor

Saehan Park


INTEGRATED CIRCUIT DEVICES INCLUDING BACKSIDE POWER RAIL AND METHODS OF FORMING THE SAME (17936106)

Main Inventor

MYUNGHOON JUNG


SEMICONDUCTOR DEVICE (18347512)

Main Inventor

Jinnam Kim


SEMICONDUCTOR PACKAGE AND ELECTRONIC DEVICE INCLUDING THE SAME (18090856)

Main Inventor

Yunseok Choi


SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME (18094786)

Main Inventor

Sungsik PARK


SEMICONDUCTOR DEVICE (18082886)

Main Inventor

Dongjoo CHOI


SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE (18218909)

Main Inventor

Sangkyu Lee


SEMICONDUCTOR PACKAGE (18091072)

Main Inventor

Eunsu LEE


IMAGE SENSORS INCLUDING META-STRUCTURE FOR COLOR SEPARATION AND ELECTRONIC DEVICES INCLUDING IMAGE SENSOR (18142219)

Main Inventor

Sungmo AHN


IMAGE SENSOR (18067393)

Main Inventor

Seonghoon KO


IMAGE SENSOR (18164228)

Main Inventor

Junghye Kim


SEMICONDUCTOR DEVICE (18079537)

Main Inventor

Seung Min SONG


SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME (18350187)

Main Inventor

GYUHWAN AHN


SEMICONDUCTOR DEVICES AND METHOD OF MANUFACTURING THE SAME (18348904)

Main Inventor

Jongsoon PARK


3D-STACKED SEMICONDUCTOR DEVICE HAVING DIFFERENT CHANNEL AND GATE DIMENSIONS ACROSS LOWER STACK AND UPPER STACK (17945695)

Main Inventor

Keumseok PARK


3D-STACKED SEMICONDUCTOR DEVICE HAVING DIFFERENT CHANNEL LAYER INTERVALS AT LOWER NANOSHEET TRANSISTOR AND UPPER NANOSHEET TRANSISTOR (17965551)

Main Inventor

Gunho JO


SEMICONDUCTOR DEVICE (18347090)

Main Inventor

Cho-eun LEE


SEMICONDUCTOR DEVICES (18107793)

Main Inventor

Hongsik Shin


SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME (18219525)

Main Inventor

Eunae CHO


SEMICONDUCTOR DEVICE (18296511)

Main Inventor

Hojun KIM


SEMICONDUCTOR DEVICE (17989944)

Main Inventor

Deok Han BAE


DISPLAY MODULE (18197847)

Main Inventor

Sangmoo PARK


ANTENNA STRUCTURE HAVING A CONDUCTIVE LAYER, AND AN ELECTRONIC DEVICE INCLUDING SAME (18219348)

Main Inventor

Wonseob KIM


SLIDABLE ELECTRONIC DEVICE INCLUDING FLEXIBLE DISPLAY AND ANTENNA (18346557)

Main Inventor

Seongyong AN


ANTENNA AND ELECTRONIC DEVICE COMPRISING SAME (18350334)

Main Inventor

Sangwon LEE


VEHICULAR ANTENNA DEVICE (18347106)

Main Inventor

Sangbong SUNG


MOTOR AND CLEANER COMPRISING THE SAME (18349689)

Main Inventor

Woong HWANG


MEMORY DEVICE AND OPERATING METHOD OF A MEMORY DEVICE (18219254)

Main Inventor

Mingyu LEE


ELECTRONIC DEVICE AND METHOD FOR CONTROLLING TRANSMISSION POWER OF COMMUNICATION MODULE (18350261)

Main Inventor

Hyeongwoo KIM


HIGH FREQUENCY TRANSMITTER AND RECEIVER RADIO FREQUENCY INTERFACE INCLUDING TRANSMIT/RECEIVE SWITCH WITH ELECTROSTATIC DISCHARGE PROTECTION AND BIASING SCHEMES (17864044)

Main Inventor

Ying CHEN


DISTRIBUTED CLOSED-LOOP POWER CONTROL WITH VGA GAIN UPDATE (17731251)

Main Inventor

Yanru TANG


DEVICE AND SYSTEM CHARACTERIZED BY MEASUREMENT, REPORT, AND CHANGE PROCEDURE BY TERMINAL FOR CHANGING TRANSMISSION/RECEPTION POINT, AND BASE STATION PROCEDURE FOR SUPPORTING SAME (18341374)

Main Inventor

Byounghoon JUNG


APPARATUS FOR ANTENNA SWITCHING IN WIRELESS COMMUNICATION SYSTEM AND OPERATING METHOD THEREOF (18180424)

Main Inventor

Hongsik Yoon


METHOD AND APPARATUS FOR IMPROVING RELIABILITY OF PHYSICAL DOWNLINK CONTROL CHANNEL IN WIRELESS NETWORK (18016938)

Main Inventor

Dhivagar BASKARAN


METHOD AND APPARATUS FOR SRS CONFIGURATION (18185340)

Main Inventor

Md. Saifur Rahman


OFDM-BASED METHOD AND DEVICE FOR SPREADING AND TRANSMITTING COMPRESSED DATA (17998625)

Main Inventor

Hyoungju JI


USER EQUIPMENT, BASE STATION AND METHOD PERFORMED BY THE SAME (18322186)

Main Inventor

Liying ZHOU


METHODS AND APPARATUS FOR CONFIGURING A ROUTE SELECTION POLICY (18191235)

Main Inventor

Jungshin PARK


VECTOR-BASED PACKET PROCESSING METHOD AND APPARATUS IN USER PLANE FUNCTION (18345411)

Main Inventor

Jihwan SEO


IOT DEVICE AND METHOD FOR ONBOARDING IOT DEVICE TO SERVER (18350996)

Main Inventor

Eunchul KIM


ELECTRONIC DEVICE AND METHOD FOR AUTHENTICATION IN SESSION INITIATION PROTOCOL (18171054)

Main Inventor

Duy Bach NGO


METHOD AND ELECTRONIC DEVICE FOR PROVIDING SEAMLESS CONTINUITY OF DATA CHANNEL SESSION (18309216)

Main Inventor

Madhusudan Gorur MANJUNATH


ELECTRONIC DEVICES AND METHODS FOR PROVIDING VIDEO CALLS (18220390)

Main Inventor

Eunsu JEONG


METHOD OF PERFORMING COMMUNICATION LOAD BALANCING WITH MULTI-TEACHER REINFORCEMENT LEARNING, AND AN APPARATUS FOR THE SAME (18351201)

Main Inventor

Jikun KANG


HINGE STRUCTURE AND ELECTRONIC DEVICE COMPRISING SAME (18348776)

Main Inventor

Yonghwa HAN


METHOD AND ELECTRONIC DEVICE FOR REMOVING ECHO FLOWING IN DUE TO EXTERNAL DEVICE (18349374)

Main Inventor

Seunghyun KIM


DEVICE AND METHOD FOR RECOVERING LOST INFORMATION IN WIRELESS COMMUNICATION SYSTEM (18349534)

Main Inventor

Taehoon LEE


IMAGE ENCODING AND DECODING METHOD USING BIDIRECTIONAL PREDICTION, AND IMAGE ENCODING AND DECODING APPARATUS (18346610)

Main Inventor

Seungsoo JEONG


IMAGE ENCODING AND DECODING METHOD USING BIDIRECTIONAL PREDICTION, AND IMAGE ENCODING AND DECODING APPARATUS (18346697)

Main Inventor

Seungsoo JEONG


IMAGE ENCODING AND DECODING METHOD USING BIDIRECTIONAL PREDICTION, AND IMAGE ENCODING AND DECODING APPARATUS (18346704)

Main Inventor

Seungsoo JEONG


VIDEO FRAME RATE CONVERSION METHOD SUPPORTING REPLACEMENT OF MOTION-COMPENSATED FRAME INTERPOLATION WITH LINEAR COMBINATION OF FRAMES AND DEVICE IMPLEMENTING THE SAME (18140932)

Main Inventor

Petr POHL


STORAGE OF EVC DECODER CONFIGURATION INFORMATION (18351219)

Main Inventor

Youngkwon Lim


ELECTRONIC DEVICE CAPABLE OF ADJUSTING ANGLE OF VIEW AND OPERATING METHOD THEREFOR (18349398)

Main Inventor

Jaehee JEON


METHOD OF BINNING IMAGE SENSOR, AND IMAGE SENSOR PERFORMING THE SAME (18093531)

Main Inventor

Chanyoung JANG


INTEGRATED HIGH-SPEED IMAGE SENSOR AND OPERATION METHOD THEREOF (18347314)

Main Inventor

Woo-Shik KIM


PIXEL AND IMAGE SENSOR INCLUDING THE SAME (18350461)

Main Inventor

Seokyong PARK


AUDIO DEVICE WITH CONNECTION TERMINAL AND SENSOR (18220875)

Main Inventor

Hongki KIM


BAYESIAN OPTIMIZATION FOR SIMULTANEOUS DECONVOLUTION OF ROOM IMPULSE RESPONSES (18054059)

Main Inventor

Sunil Bharitkar


METHOD AND SYSTEM FOR IMPROVEMENTS IN AND RELATING TO MICROSERVICES FOR MEC NETWORKS (17793296)

Main Inventor

Walter FEATHERSTONE


APPARATUS AND METHOD FOR TRANSMITTING OR RECEIVING MESSAGE BY USING BLUETOOTH LOW ENERGY ADVERTISING (18140413)

Main Inventor

Taejun KWON


METHOD AND APPARATUS FOR IDENTIFYING IN-CALL CAPABILITY FEATURES (18349824)

Main Inventor

Chandrashekhar BYADGI


METHOD AND APPARATUS FOR AUTHENTICATION OF INTEGRATED ACCESS AND BACKHAUL (IAB) NODE IN WIRELESS NETWORK (18339118)

Main Inventor

Rajavelsamy RAJADURAI


METHOD AND DEVICE FOR AUTHENTICATING UE (18346023)

Main Inventor

Hong WANG


METHODS AND SYSTEMS FOR IDENTIFYING AUSF AND ACCESSING RELATED KEYS IN 5G PROSE (18017002)

Main Inventor

R ROHINI


METHOD AND APPARATUS FOR PROCESSING DATA FOR PACKET DUPLICATION (18349816)

Main Inventor

Sangkyu BAEK


SYSTEM AND METHOD TO SEGMENT RECOVERY AND MESSAGE FEEDBACK IN 5G MESSAGING ARCHITECTURE (17925198)

Main Inventor

Basavaraj Jayawant PATTAN


APPARATUS AND METHOD FOR SUPPORTING HANDOVER IN A WIRELESS COMMUNICATION SYSTEM (18330744)

Main Inventor

Lixiang XU


METHOD AND DEVICE FOR SWITCHING A SERVING CELL AND METHOD AND DEVICE SUPPORTING ON-DEMAND SYSTEM INFORMATION MESSAGE (18348810)

Main Inventor

Weiwei WANG


METHOD AND APPARATUS FOR PERFORMING CONDITIONAL PSCELL CHANGE PROCEDURE IN NEXT-GENERATION MOBILE COMMUNICATION SYSTEM (17998630)

Main Inventor

Sangyeob JUNG


DEVICE AND METHOD FOR CELL MANAGEMENT IN RADIO ACCESS NETWORKS (18305838)

Main Inventor

Minsung CHO


MOBILITY IN NON-TERRESTRIAL NETWORKS WITH EARTH MOVING CELLS (18186800)

Main Inventor

Shiyang Leng


METHOD AND DEVICE FOR SAVING ENERGY IN WIRELESS COMMUNICATION SYSTEM (18305696)

Main Inventor

Junyung YI


METHOD AND APPARATUS FOR SAVING POWER OF USER EQUIPMENT IN WIRELESS COMMUNICATION SYSTEM (18349540)

Main Inventor

Taehyoung KIM


ELECTRONIC DEVICE TRANSMITTING UPLINK SIGNAL AND OPERATING METHOD THEREOF (18348796)

Main Inventor

Janggun BAE


ELECTRONIC DEVICE AND METHOD FOR CONTROLLING TRANSMISSION POWER BASED ON BLUETOOTH COMMUNICATION IN ELECTRONIC DEVICE (18351168)

Main Inventor

Insik LEE


METHODS AND APPARATUS FOR ROUND-TRIP-TIME MEASUREMENT ON A SL INTERFACE (18303350)

Main Inventor

Emad N. Farag


METHOD AND APPARATUS FOR RESOURCE ALLOCATION FOR SIDELINK POSITIONING IN A WIRELESS COMMUNICATION SYSTEM (18138881)

Main Inventor

Miao ZHOU


LATENCY REDUCTION FOR TRANSMISSION OR RECEPTION OF DATA (18299629)

Main Inventor

Aris Papasakellariou


PDCCH FOR MULTI-CELL SCHEDULING (18301848)

Main Inventor

Ebrahim MolavianJazi


METHOD AND APPARATUS FOR GRANT-FREE DATA TRANSMISSION IN WIRELESS COMMUNICATION SYSTEM (18346519)

Main Inventor

Sungjin PARK


TRANSMISSION METHOD AND APPARATUS FOR MIMO SYSTEM (18349561)

Main Inventor

Jonghwan KIM


TRANSMISSION METHOD AND APPARATUS FOR MIMO SYSTEM (18349585)

Main Inventor

Jonghwan KIM


METHOD AND APPARATUS FOR HANDLING MSGA RETRANSMISSIONS DURING TWO STEP RANDOM ACCESS PROCEDURES IN WIRELESS COMMUNICATION SYSTEM (18345195)

Main Inventor

Anil AGIWAL


SYSTEM AND METHOD OF SELECTING RACH OCCASIONS FOR SYSTEM INFORMATION REQUEST (18346603)

Main Inventor

Anil AGIWAL


METHOD AND APPARATUS FOR RECOVERY FROM FALLBACK FOR CELLULAR INTERNET OF THINGS DEVICE (17796472)

Main Inventor

Mahmoud WATFA


CIRCUIT BOARD AND ELECTRONIC DEVICE INCLUDING CIRCUIT BOARD (17904220)

Main Inventor

Bumhee BAE


FLEXIBLE CIRCUIT BOARD AND ELECTRONIC DEVICE COMPRISING SAME (18348622)

Main Inventor

Youngsun LEE


ELECTRONIC DEVICE INCLUDING FLEXIBLE PRINTED CIRCUIT BOARD (18346880)

Main Inventor

Yongyoun KIM


COVER PLATE FOR ELECTRONIC DEVICE AND ELECTRONIC DEVICE COMPRISING SAME (18348661)

Main Inventor

Hwanju JEON


INTEGRATED CIRCUIT DEVICES INCLUDING A POWER DISTRIBUTION NETWORK AND METHODS OF FORMING THE SAME (17816809)

Main Inventor

Inchan Hwang


SEMICONDUCTOR DEVICES (18115116)

Main Inventor

Minjun Lee


SEMICONDUCTOR DEVICE (18062825)

Main Inventor

Kiseok Lee


SEMICONDUCTOR DEVICE (18304930)

Main Inventor

Yoongoo Kang


SEMICONDUCTOR MEMORY DEVICE (18117604)

Main Inventor

Kiseok LEE


SEMICONDUCTOR DEVICES (18220323)

Main Inventor

Dongoh KIM


SEMICONDUCTOR DEVICES (18220327)

Main Inventor

Dongoh KIM


VERTICAL MEMORY DEVICES (18220073)

Main Inventor

DONGHWAN KIM


SEMICONDUCTOR DEVICES INCLUDING STACK STRUCTURE HAVING GATE REGION AND INSULATING REGION (18348521)

Main Inventor

Geunwon LIM


SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME (18072312)

Main Inventor

SEUNGMIN LEE


SEMICONDUCTOR MEMORY DEVICE (18175198)

Main Inventor

Teawon KIM


SEMICONDUCTOR MEMORY DEVICE (18104882)

Main Inventor

Yong Jae LEE


SEMICONDUCTOR MEMORY DEVICE (18113717)

Main Inventor

Jong Hyun PAEK


VARIABLE RESISTANCE MEMORY DEVICE (18104890)

Main Inventor

Sung-Ho EUN


PHOTOELECTRIC CONVERSION DEVICE AND SENSOR AND ELECTRONIC DEVICE (18347960)

Main Inventor

Daiki MINAMI


SEMICONDUCTOR APPARATUS (18349433)

Main Inventor

Kiyeon YANG

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