US Patent Application 17945695. 3D-STACKED SEMICONDUCTOR DEVICE HAVING DIFFERENT CHANNEL AND GATE DIMENSIONS ACROSS LOWER STACK AND UPPER STACK simplified abstract
3D-STACKED SEMICONDUCTOR DEVICE HAVING DIFFERENT CHANNEL AND GATE DIMENSIONS ACROSS LOWER STACK AND UPPER STACK
Organization Name
Inventor(s)
Keumseok Park of Slingerlands NY (US)
Sooyoung Park of Halfmoon NY (US)
Kang-ill Seo of Springfield VA (US)
3D-STACKED SEMICONDUCTOR DEVICE HAVING DIFFERENT CHANNEL AND GATE DIMENSIONS ACROSS LOWER STACK AND UPPER STACK - A simplified explanation of the abstract
This abstract first appeared for US patent application 17945695 titled '3D-STACKED SEMICONDUCTOR DEVICE HAVING DIFFERENT CHANNEL AND GATE DIMENSIONS ACROSS LOWER STACK AND UPPER STACK
Simplified Explanation
The abstract describes a multi-stack semiconductor device that includes a lower-stack nanosheet transistor and an upper-stack nanosheet transistor. The lower-stack transistor has multiple lower channel layers connected by a lower gate structure, while the upper-stack transistor has multiple upper channel layers connected by an upper gate structure. The thickness of the channel layers and gate structures may differ between the lower-stack and upper-stack transistors.
Bullet points:
- The multi-stack semiconductor device includes a lower-stack nanosheet transistor and an upper-stack nanosheet transistor. - The lower-stack transistor consists of multiple lower channel layers connected by a lower gate structure. - The upper-stack transistor consists of multiple upper channel layers connected by an upper gate structure. - There may be a difference in thickness between the lower channel layers and the upper channel layers. - There may also be a difference in thickness between the lower gate structure and the upper gate structure. - The purpose of these differences in thickness is not specified in the abstract.
Original Abstract Submitted
Provided is a multi-stack semiconductor device including: a substrate; a lower-stack nanosheet transistor including two or more lower channel layers surrounded by a lower gate structure, the lower channel layers connecting lower source/drain regions; and an upper-stack nanosheet transistor formed above the lower-stack nanosheet transistor, and including two or more upper channel layers surrounded by an upper gate structure, the upper channel layers connecting upper source/drain regions, wherein the lower-stack nanosheet transistor and the upper-stack nanosheet transistor have at least one of: a difference between a thickness of one of the lower channel layers and a thickness of one of the upper channel layers; and a difference between a thickness of the lower gate structure between two adjacent lower channel layers and a thickness of the upper gate structure between two adjacent upper channel layers.
