US Patent Application 18140974. MEMORY DEVICE INCLUDING ADDRESS TABLE AND OPERATING METHOD FOR MEMORY CONTROLLER simplified abstract

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MEMORY DEVICE INCLUDING ADDRESS TABLE AND OPERATING METHOD FOR MEMORY CONTROLLER

Organization Name

Samsung Electronics Co., Ltd.


Inventor(s)

CHINAM Kim of SUWON-SI (KR)


TAEKYEONG Ko of SUWON-SI (KR)


NAMHYUNG Kim of SUWON-SI (KR)


DOHAN Kim of SUWON-SI (KR)


BYEONGNOH Kim of SUWON-SI (KR)


BOBAE Kim of SUWON-SI (KR)


CHANGMIN Lee of SUWON-SI (KR)


KYEONGJIN Cho of SUWON-SI (KR)


INSU Choi of SUWON-SI (KR)


MEMORY DEVICE INCLUDING ADDRESS TABLE AND OPERATING METHOD FOR MEMORY CONTROLLER - A simplified explanation of the abstract

  • This abstract for appeared for US patent application number 18140974 Titled 'MEMORY DEVICE INCLUDING ADDRESS TABLE AND OPERATING METHOD FOR MEMORY CONTROLLER'

Simplified Explanation

This abstract describes a memory device that includes a memory cell array and a command/address decoder. The decoder has a buffer memory and two decoding logic circuits. The decoder is able to decrypt various commands and address information received from a memory controller. It can decrypt a table synchronization command, store an address table in the buffer memory, decrypt a table-based command with associated index information, and execute the command on a specific address. Overall, this memory device is designed to efficiently handle and process commands and address information from a memory controller.


Original Abstract Submitted

A memory device includes; a memory cell array, and a command/address decoder including a buffer memory, a first decoding logic circuit configured to decrypt command/address information, and a second decoding logic circuit configured to decrypt an address table. The command/address decoder is configured to decrypt a first command received from a memory controller through the first decoding logic circuit to obtain a table synchronization command, decrypt data received from the memory controller after a predefined latency from receipt of the first command through the second decoding logic circuit to obtain an address table, store the address table in the buffer memory, decrypt a second command received from the memory controller through the first decoding logic circuit to obtain a table-based command and index information associated with the address table, and execute the table-based command with respect to an address corresponding to the index information.