US Patent Application 18220323. SEMICONDUCTOR DEVICES simplified abstract

SEMICONDUCTOR DEVICES

Organization Name

Samsung Electronics Co., Ltd.

Inventor(s)

Dongoh Kim of Daegu (KR)

Gyuhyun Kil of Hwaseong-si (KR)

Junghoon Han of Hwaseong-si (KR)

Doosan Back of Seoul (KR)

SEMICONDUCTOR DEVICES - A simplified explanation of the abstract

This abstract first appeared for US patent application 18220323 titled 'SEMICONDUCTOR DEVICES

Simplified Explanation

The patent application describes a semiconductor device that includes two trenches in a substrate, with isolation structures and gate structures stacked in each trench.

• The device has first and second trenches in a substrate, with isolation structures and gate structures stacked in each trench.
• The first trench has a first inner wall oxide pattern, a first liner, and a first filling insulation pattern stacked in sequence.
• The second trench has a second inner wall oxide pattern, a second liner, and a second filling insulation pattern stacked in sequence.
• The first and second gate structures are stacked on the first and second regions, respectively.
• The first gate structure includes a first high-k dielectric pattern, a first P-type metal pattern, and a first N-type metal pattern.
• The second gate structure includes a second high-k dielectric pattern and a second N-type metal pattern.
• The first and second liners protrude above the upper surfaces of the inner wall oxide patterns and filling insulation patterns.

Original Abstract Submitted

A semiconductor device includes first and second trenches in respective first and second regions in a substrate, a first isolation structure having a first inner wall oxide pattern, a first liner, and a first filling insulation pattern sequentially stacked I the first trench, a second isolation structure having a second inner wall oxide pattern, a second liner, and a second filling insulation pattern sequentially stacked I the second trench, a first gate structure having a first high-k dielectric pattern, a first P-type metal pattern, and a first N-type metal pattern sequentially stacked on the first region, and a second gate structure having a second high-k dielectric pattern and a second N-type metal pattern sequentially stacked on the second region, wherein the first and second liners protrude above upper surfaces of the first and second inner wall oxide patterns and the first and second filling insulation patterns, respectively.