US Patent Application 18218909. SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE simplified abstract
Contents
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18218909 titled 'SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE
Simplified Explanation
The abstract describes a semiconductor package that includes a support member, a semiconductor chip, lower and upper redistribution wiring layers, and a thermal pattern.
- The semiconductor package has a support member that holds the components together. - A semiconductor chip is placed in the support member, with its front surface and backside surface exposed. - The lower redistribution wiring layer covers the second surface of the support member and includes first redistribution wirings that connect the chip pads on the front surface of the semiconductor chip and vertical connection structures of the support member. - The upper redistribution wiring layer covers the first surface of the support member and includes second redistribution wirings that connect the vertical connection structures and a thermal pattern on the backside surface of the semiconductor chip. - The thermal pattern helps with heat dissipation from the semiconductor chip. - The arrangement of the support member, semiconductor chip, and redistribution wiring layers provides an improved structure for the semiconductor package.
Original Abstract Submitted
A semiconductor package includes a support member, a semiconductor chip arranged in the support member such that a front surface and a backside surface of the semiconductor chip are exposed from a second surface of the support member and a first surface opposite to the second surface respectively, a lower redistribution wiring layer covering the second surface of the support member and including first redistribution wirings electrically connected to chip pads provided at the front surface of the semiconductor chip and vertical connection structures of the support member respectively, and an upper redistribution wiring layer covering the first surface of the support substrate, and including second redistribution wirings electrically connected to the vertical connection structures and a thermal pattern provided on the exposed backside surface of the semiconductor chip.
