US Patent Application 18104890. VARIABLE RESISTANCE MEMORY DEVICE simplified abstract

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VARIABLE RESISTANCE MEMORY DEVICE

Organization Name

Samsung Electronics Co., Ltd.


Inventor(s)

Sung-Ho Eun of Suwon-si (KR)

Yu Na Gil of Suwon-si (KR)

Su Min Yu of Suwon-si (KR)

VARIABLE RESISTANCE MEMORY DEVICE - A simplified explanation of the abstract

This abstract first appeared for US patent application 18104890 titled 'VARIABLE RESISTANCE MEMORY DEVICE

Simplified Explanation

The patent application describes a variable resistance memory device.

  • The device includes a substrate, a cell array region, a wiring region, an upper wiring structure, and a protective film.
  • The cell array region contains multiple memory cells.
  • The wiring region has an inter-wiring insulating film stacked on the cell array region.
  • The upper wiring structure is located in the inter-wiring insulating film.
  • The protective film covers the upper surface of the cell array region.
  • Each memory cell consists of a switching pattern and a variable resistance pattern.
  • The cell array region has first conductive lines extending in one direction and second conductive lines extending in a different direction.
  • The memory cells are located at the intersections of the first and second conductive lines.


Original Abstract Submitted

A variable resistance memory device includes a substrate, a cell array region including a plurality of memory cells on the substrate, a wiring region which includes an inter-wiring insulating film stacked on the cell array region, and an upper wiring structure in the inter-wiring insulating film and a protective film which covers an upper surface of the cell array region, between the cell array region and the wiring region, wherein each of the memory cells includes a switching pattern and a variable resistance pattern, the cell array region further includes first conductive lines extending in a first direction, and a second conductive lines extending in a second direction intersecting the first direction, and the plurality of memory cells are disposed at an intersections of the first conductive lines and the second conductive lines.