US Patent Application 18117604. SEMICONDUCTOR MEMORY DEVICE simplified abstract

From WikiPatents
Jump to navigation Jump to search

SEMICONDUCTOR MEMORY DEVICE

Organization Name

Samsung Electronics Co., Ltd.


Inventor(s)

Kiseok Lee of Suwon-si (KR)

Junhyeok Ahn of Suwon-si (KR)

Keunnam Kim of Suwon-si (KR)

Chan-Sic Yoon of Suwon-si (KR)

Myeong-Dong Lee of Suwon-si (KR)

SEMICONDUCTOR MEMORY DEVICE - A simplified explanation of the abstract

This abstract first appeared for US patent application 18117604 titled 'SEMICONDUCTOR MEMORY DEVICE

Simplified Explanation

The patent application describes a semiconductor memory device.

  • The device includes a semiconductor substrate with an active portion defined by a device isolation layer.
  • A bit line structure intersects the active portion on the substrate.
  • A first conductive pad is located between the bit line structure and the active portion.
  • A bit line contact pattern is positioned between the first conductive pad and the bit line structure.
  • A first bit line contact spacer covers one side of the first conductive pad, while a second bit line contact spacer covers the other side.
  • The first conductive pad has a flat bottom surface that contacts the top surface of the active portion.
  • The width of the first bit line contact spacer is different from the width of the second bit line contact spacer.


Original Abstract Submitted

A semiconductor memory device includes a semiconductor substrate; a device isolation layer defining an active portion in the semiconductor substrate; a bit line structure intersecting the active portion on the semiconductor substrate; a first conductive pad between the bit line structure and the active portion; a bit line contact pattern between the first conductive pad and the bit line structure; a first bit line contact spacer covering a first sidewall of the first conductive pad; and a second bit line contact spacer covering a second sidewall of the first conductive pad, wherein the first conductive pad has a flat bottom surface that is in contact with a top surface of the active portion, and a width of the first bit line contact spacer is different from a width of the second bit line contact spacer.