US Patent Application 17816809. INTEGRATED CIRCUIT DEVICES INCLUDING A POWER DISTRIBUTION NETWORK AND METHODS OF FORMING THE SAME simplified abstract

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INTEGRATED CIRCUIT DEVICES INCLUDING A POWER DISTRIBUTION NETWORK AND METHODS OF FORMING THE SAME

Organization Name

Samsung Electronics Co., Ltd.


Inventor(s)

Inchan Hwang of Schenectady NY (US)

Jaemyung Choi of Niskayuna NY (US)

Kangill Seo of Albany NY (US)

INTEGRATED CIRCUIT DEVICES INCLUDING A POWER DISTRIBUTION NETWORK AND METHODS OF FORMING THE SAME - A simplified explanation of the abstract

This abstract first appeared for US patent application 17816809 titled 'INTEGRATED CIRCUIT DEVICES INCLUDING A POWER DISTRIBUTION NETWORK AND METHODS OF FORMING THE SAME

Simplified Explanation

The patent application describes integrated circuit devices and methods for their formation, specifically focusing on a static random access memory (SRAM) unit.

  • The SRAM unit includes a first inverter on a substrate and a power distribution network (PDN) structure with a first power rail and a second power rail.
  • The substrate extends between the first inverter and the PDN structure.
  • The first inverter consists of a first upper transistor with a first upper source/drain region, a first lower transistor between the substrate and the first upper transistor with a first lower source/drain region.
  • There is a first power contact that extends through the substrate and connects the first upper source/drain region to the first power rail.
  • Additionally, there is a second power contact that extends through the substrate and connects the first lower source/drain region to the second power rail.


Original Abstract Submitted

Integrated circuit devices and methods of forming the same are provided. The integrated circuit devices may include a static random access memory (SRAM) unit. The SRAM unit may include a first inverter on a substrate and a power distribution network (PDN) structure including a first power rail and a second power rail. The substrate may extend between the first inverter and the PDN structure. The first inverter may include a first upper transistor including a first upper source/drain region, a first lower transistor between the substrate and the first upper transistor and including a first lower source/drain region, a first power contact extending through the substrate and electrically connecting the first upper source/drain region to the first power rail, and a second power contact extending through the substrate and electrically connecting the first lower source/drain region to the second power rail.