US Patent Application 18091072. SEMICONDUCTOR PACKAGE simplified abstract

From WikiPatents
Jump to navigation Jump to search

SEMICONDUCTOR PACKAGE

Organization Name

Samsung Electronics Co., Ltd.


Inventor(s)

Eunsu Lee of Suwon-si (KR)


Jangwoo Lee of Suwon-si (KR)


Doyoung Jang of Suwon-si (KR)


SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract

This abstract first appeared for US patent application 18091072 titled 'SEMICONDUCTOR PACKAGE

Simplified Explanation

The abstract describes a semiconductor package that includes a first package substrate, a semiconductor chip, an interposer, and a vertical conductive structure. The interposer is positioned on the semiconductor chip and connects the first package substrate and the interposer. The interposer has a recess that overlaps with the semiconductor chip, and the lower surface of the interposer is higher than the upper surface of the vertical conductive structure.

- The semiconductor package includes a first package substrate, a semiconductor chip, an interposer, and a vertical conductive structure. - The interposer is placed on the semiconductor chip and acts as a connection between the first package substrate and the interposer. - The interposer has a recess that vertically overlaps with the semiconductor chip. - The lower surface of the interposer, which defines the recess, is positioned higher than the upper surface of the vertical conductive structure.


Original Abstract Submitted

A semiconductor package includes a first package substrate, a first semiconductor chip provided on the first package substrate, an interposer provided on the first semiconductor chip, and a vertical conductive structure provided on the first package substrate and a side surface of the first semiconductor chip, and connecting the first package substrate and the interposer, the interposer includes a first recess vertically overlapping the first semiconductor chip in a lower portion of the interposer, and a lower surface of the interposer defining the first recess is higher than an upper surface of the vertical conductive structure.