US Patent Application 18219254. MEMORY DEVICE AND OPERATING METHOD OF A MEMORY DEVICE simplified abstract
Contents
MEMORY DEVICE AND OPERATING METHOD OF A MEMORY DEVICE
Organization Name
Inventor(s)
Youngchul Cho of Suwon-si (KR)
Seungjin Park of Suwon-si (KR)
Youngdon Choi of Suwon-si (KR)
Junghwan Choi of Suwon-si (KR)
MEMORY DEVICE AND OPERATING METHOD OF A MEMORY DEVICE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18219254 titled 'MEMORY DEVICE AND OPERATING METHOD OF A MEMORY DEVICE
Simplified Explanation
The abstract describes a clock signal delay path unit in a clock signal transmission system. It includes multiple delay cells and repeaters to delay and transmit clock signals without signal attenuation.
- The clock signal delay path unit consists of a first delay cell, a first repeater, a second root signal line, a second delay cell, a first inverting circuit, a third delay cell, a second repeater, and a second branch signal line. - The first delay cell delays and transmits a clock signal through a first root signal line. - The first repeater transmits the clock signal without signal attenuation. - The second root signal line delays and transmits the clock signal output from the first repeater. - The second delay cell inverts the clock signal provided from the first delay cell to generate an inverted clock signal. - The first inverting circuit is part of the second delay cell and performs the inversion of the clock signal. - The third delay cell delays and transmits the inverted clock signal through a first branch signal line. - The second repeater transmits the inverted clock signal without signal attenuation. - The second branch signal line delays and transmits the inverted clock signal output from the second repeater.
Original Abstract Submitted
A clock signal delay path unit includes a first delay cell including a first root signal line for delaying and transmitting a clock signal, a first repeater to transmit the clock signal transmitted through the first root signal line without signal attenuation, and a second root signal line for delaying and transmitting the clock signal output from the first repeater, a second delay cell including a first inverting circuit configured to invert the clock signal provided from the first delay cell to generate an inverted clock signal, and a third delay cell including a first branch signal line for delaying and transmitting the inverted clock signal provided from the second delay cell, a second repeater to transmit the inverted clock signal transmitted through the first branch signal line, and a second branch signal line for delaying and transmitting the inverted clock signal output from the second repeater.
