US Patent Application 18175198. SEMICONDUCTOR MEMORY DEVICE simplified abstract

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SEMICONDUCTOR MEMORY DEVICE

Organization Name

Samsung Electronics Co., Ltd.


Inventor(s)

Teawon Kim of Suwon-si (KR)

Yurim Kim of Suwon-si (KR)

Seunghee Lee of Suwon-si (KR)

Seungwoo Jang of Suwon-si (KR)

Yong-Suk Tak of Suwon-si (KR)

SEMICONDUCTOR MEMORY DEVICE - A simplified explanation of the abstract

This abstract first appeared for US patent application 18175198 titled 'SEMICONDUCTOR MEMORY DEVICE

Simplified Explanation

The patent application describes a semiconductor memory device that includes a bit line, a channel pattern, a word line, and a gate insulating pattern.

  • The channel pattern consists of a horizontal channel portion on the bit line and a vertical channel portion that extends vertically from the horizontal channel portion.
  • The word line is located on the horizontal channel portion and on the sidewall of the vertical channel portion.
  • A gate insulating pattern is positioned between the word line and the channel pattern.
  • The channel pattern is made of an oxide semiconductor and is composed of three sequentially stacked layers: first, second, and third channel layers.
  • The first to third channel layers contain a first metal, while the second channel layer also includes a second metal that is different from the first metal.
  • At least a portion of the first channel layer makes contact with the bit line.


Original Abstract Submitted

A semiconductor memory device includes a bit line, a channel pattern including a horizontal channel portion on the bit line and a vertical channel portion vertically protruding from the horizontal channel portion, a word line on the horizontal channel portion and on a sidewall of the vertical channel portion, and a gate insulating pattern between the word line and the channel pattern. The channel pattern includes an oxide semiconductor and includes first, second, and third channel layers sequentially stacked. The first to third channel layers include a first metal, and the second channel layer further includes a second metal different from the first metal. At least a portion of the first channel layer contacts the bit line.