US Patent Application 18107793. SEMICONDUCTOR DEVICES simplified abstract
Contents
SEMICONDUCTOR DEVICES
Organization Name
Inventor(s)
Jeongyeon Seo of Suwon-si (KR)
Kyungyub Jeon of Suwon-si (KR)
SEMICONDUCTOR DEVICES - A simplified explanation of the abstract
This abstract first appeared for US patent application 18107793 titled 'SEMICONDUCTOR DEVICES
Simplified Explanation
The abstract describes a semiconductor device that includes multiple gate structures, contact plug structures, and wiring on a substrate. The device also has source/drain layers formed adjacent to the gate structures. The first gate structure has a gate electrode and insulation pattern, while the second gate structure has a different gate electrode and insulation pattern. The second gate electrode is positioned lower than the first gate electrode.
Key points of the patent/innovation:
- The semiconductor device has multiple gate structures, allowing for more complex circuitry and functionality. - The gate structures have different gate electrodes and insulation patterns, providing flexibility in design and performance. - The source/drain layers are formed adjacent to the gate structures, enabling efficient electrical connections. - Contact plug structures are formed on the source/drain layers, facilitating further electrical connections. - The first gate structure's upper surface is contacted by a wiring, allowing for signal transmission and integration with other components. - The second gate structure's upper surface is positioned lower than the first gate structure, potentially reducing interference and improving performance.
Original Abstract Submitted
A semiconductor device includes first and second gate structures, first and second contact plug structures and a first wiring on a substrate. The first and second source/drain layers are formed on portions of the substrate adjacent to the first and second gate structures, respectively. The first and second contact plug structures are formed on the first and second source/drain layers, respectively. The first wiring contacts an upper surface of the first gate structure. The first gate structure includes a first gate electrode and a first gate insulation pattern on a lower surface and a sidewall of the first gate electrode. The second gate structure includes a second gate electrode and a second gate insulation pattern on a lower surface and a sidewall of the second gate electrode. The upper surface of the second gate electrode is lower than an upper surface of the first gate electrode.
